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| author | Joel Hestness <jthestness@gmail.com> | 2015-08-14 00:19:45 -0500 |
|---|---|---|
| committer | Joel Hestness <jthestness@gmail.com> | 2015-08-14 00:19:45 -0500 |
| commit | 905c0b347c785d07b606b6a9f3c6bbdf8ebe96a7 (patch) | |
| tree | e04c0fe6cf9ff037281e618a808bd390c6457f5b /src/mem/protocol/MOESI_hammer-cache.sm | |
| parent | 581bae9ecbafd5e94c5405ca925a55cc6e5d7488 (diff) | |
| download | gem5-905c0b347c785d07b606b6a9f3c6bbdf8ebe96a7.tar.xz | |
ruby: Protocol changes for SimObject MessageBuffers
Diffstat (limited to 'src/mem/protocol/MOESI_hammer-cache.sm')
| -rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index badbe1d8b..04ada750e 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -46,16 +46,16 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") // NETWORK BUFFERS MessageBuffer * requestFromCache, network="To", virtual_network="2", - ordered="false", vnet_type="request"; + vnet_type="request"; MessageBuffer * responseFromCache, network="To", virtual_network="4", - ordered="false", vnet_type="response"; + vnet_type="response"; MessageBuffer * unblockFromCache, network="To", virtual_network="5", - ordered="false", vnet_type="unblock"; + vnet_type="unblock"; MessageBuffer * forwardToCache, network="From", virtual_network="3", - ordered="false", vnet_type="forward"; + vnet_type="forward"; MessageBuffer * responseToCache, network="From", virtual_network="4", - ordered="false", vnet_type="response"; + vnet_type="response"; { // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { @@ -143,7 +143,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") // STRUCTURE DEFINITIONS - MessageBuffer mandatoryQueue, ordered="false"; + MessageBuffer mandatoryQueue; // CacheEntry structure(Entry, desc="...", interface="AbstractCacheEntry") { @@ -320,7 +320,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return cache_entry.AtomicAccessed; } - MessageBuffer triggerQueue, ordered="false"; + MessageBuffer triggerQueue; // ** OUT_PORTS ** |