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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
commit5060e572ca07b98f7d84679bac81c0151dee46b9 (patch)
treed7ff69a0fb7c5959b038dad87cd01e08801f33fe /src/mem/protocol/MOESI_hammer-cache.sm
parentb815221718d246549311b2923a2da7a233e1f625 (diff)
downloadgem5-5060e572ca07b98f7d84679bac81c0151dee46b9.tar.xz
ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement policy structures with the first level caches. While functionally this is correct, the problem is that this requires calling findTagInSet() which is an expensive function. This patch removes the calls to setMRU from the sequencer. All controllers should now update the replacement policy on their own. The set and the way index for a given cache entry can be found within the AbstractCacheEntry structure. Use these indicies to update the replacement policy structures.
Diffstat (limited to 'src/mem/protocol/MOESI_hammer-cache.sm')
-rw-r--r--src/mem/protocol/MOESI_hammer-cache.sm35
1 files changed, 24 insertions, 11 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 0b7acb701..269e47dfd 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -857,9 +857,18 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
}
}
- action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
+ action(h_load_hit, "hd", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Dcache.setMRU(cache_entry);
+ sequencer.readCallback(address, cache_entry.DataBlk, false,
+ testAndClearLocalHit(cache_entry));
+ }
+
+ action(h_ifetch_hit, "hi", desc="Notify sequencer the ifetch completed.") {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Icache.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk, false,
testAndClearLocalHit(cache_entry));
}
@@ -869,7 +878,8 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
assert(is_valid(tbe));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
peek(responseToCache_in, ResponseMsg) {
-
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.readCallback(address, cache_entry.DataBlk, true,
machineIDToMachineType(in_msg.Sender), tbe.InitialRequestTime,
tbe.ForwardRequestTime, tbe.FirstResponseTime);
@@ -880,6 +890,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
peek(mandatoryQueue_in, RubyRequest) {
+ L1Dcache.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk, false,
testAndClearLocalHit(cache_entry));
@@ -901,7 +912,8 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
assert(is_valid(tbe));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
peek(responseToCache_in, ResponseMsg) {
-
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.writeCallback(address, cache_entry.DataBlk, true,
machineIDToMachineType(in_msg.Sender), tbe.InitialRequestTime,
tbe.ForwardRequestTime, tbe.FirstResponseTime);
@@ -914,7 +926,8 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
assert(is_valid(cache_entry));
assert(is_valid(tbe));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.writeCallback(address, cache_entry.DataBlk, true,
machineIDToMachineType(tbe.LastResponder), tbe.InitialRequestTime,
tbe.ForwardRequestTime, tbe.FirstResponseTime);
@@ -1508,7 +1521,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
}
transition({S, SM, ISM}, Ifetch) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileL1InstHit;
k_popMandatoryQueue;
}
@@ -1522,7 +1535,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
}
transition(SR, Ifetch, S) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileL1InstMiss;
uu_profileL2Hit;
k_popMandatoryQueue;
@@ -1570,7 +1583,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
}
transition({O, OM, SS, MM_W, M_W}, {Ifetch}) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileL1InstHit;
k_popMandatoryQueue;
}
@@ -1584,7 +1597,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
}
transition(OR, Ifetch, O) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileL1InstMiss;
uu_profileL2Hit;
k_popMandatoryQueue;
@@ -1635,7 +1648,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
// Transitions from Modified
transition({MM, M}, {Ifetch}) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileL1InstHit;
k_popMandatoryQueue;
}
@@ -1661,7 +1674,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
}
transition(MMR, Ifetch, MM) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileL1InstMiss;
uu_profileL2Hit;
k_popMandatoryQueue;
@@ -1742,7 +1755,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
}
transition(MR, Ifetch, M) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileL1InstMiss;
uu_profileL2Hit;
k_popMandatoryQueue;