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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
commitf391cee5e1f9192bc35978df236e15f921a690cf (patch)
treed691208b544b003fa7f2e163bfa5cb9c57647bea /src/mem/protocol/MOESI_hammer-cache.sm
parent1a3e8a3370f7ed904c05eef4066d46052e028d3f (diff)
downloadgem5-f391cee5e1f9192bc35978df236e15f921a690cf.tar.xz
ruby: drop the [] notation for lookup function.
This is in preparation for adding a second arugment to the lookup function for the CacheMemory class. The change to *.sm files was made using the following sed command: sed -i 's/\[\([0-9A-Za-z._()]*\)\]/.lookup(\1)/' src/mem/protocol/*.sm
Diffstat (limited to 'src/mem/protocol/MOESI_hammer-cache.sm')
-rw-r--r--src/mem/protocol/MOESI_hammer-cache.sm30
1 files changed, 15 insertions, 15 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index d5539e021..0b7acb701 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -210,7 +210,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
if(is_valid(cache_entry)) {
testAndRead(addr, cache_entry.DataBlk, pkt);
} else {
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
} else {
@@ -229,7 +229,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
return num_functional_writes;
}
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
num_functional_writes := num_functional_writes +
testAndWrite(addr, tbe.DataBlk, pkt);
return num_functional_writes;
@@ -274,7 +274,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
}
AccessPermission getAccessPermission(Addr addr) {
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
return L1Cache_State_to_permission(tbe.TBEState);
}
@@ -337,7 +337,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
peek(triggerQueue_in, TriggerMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
- TBE tbe := TBEs[in_msg.addr];
+ TBE tbe := TBEs.lookup(in_msg.addr);
if (in_msg.Type == TriggerType:L2_to_L1) {
trigger(Event:Complete_L2_to_L1, in_msg.addr, cache_entry, tbe);
@@ -360,7 +360,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
peek(responseToCache_in, ResponseMsg, block_on="addr") {
Entry cache_entry := getCacheEntry(in_msg.addr);
- TBE tbe := TBEs[in_msg.addr];
+ TBE tbe := TBEs.lookup(in_msg.addr);
if (in_msg.Type == CoherenceResponseType:ACK) {
trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
@@ -385,7 +385,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
peek(forwardToCache_in, RequestMsg, block_on="addr") {
Entry cache_entry := getCacheEntry(in_msg.addr);
- TBE tbe := TBEs[in_msg.addr];
+ TBE tbe := TBEs.lookup(in_msg.addr);
if ((in_msg.Type == CoherenceRequestType:GETX) ||
(in_msg.Type == CoherenceRequestType:GETF)) {
@@ -429,7 +429,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
- TBE tbe := TBEs[in_msg.LineAddress];
+ TBE tbe := TBEs.lookup(in_msg.LineAddress);
if (in_msg.Type == RubyRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
@@ -452,7 +452,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
trigger(Event:L2_Replacement,
l2_victim_addr,
getL2CacheEntry(l2_victim_addr),
- TBEs[l2_victim_addr]);
+ TBEs.lookup(l2_victim_addr));
}
}
@@ -477,14 +477,14 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
trigger(Event:L1_to_L2,
l1i_victim_addr,
getL1ICacheEntry(l1i_victim_addr),
- TBEs[l1i_victim_addr]);
+ TBEs.lookup(l1i_victim_addr));
} else {
Addr l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr);
// The L2 does not have room, so we replace a line from the L2
trigger(Event:L2_Replacement,
l2_victim_addr,
getL2CacheEntry(l2_victim_addr),
- TBEs[l2_victim_addr]);
+ TBEs.lookup(l2_victim_addr));
}
}
}
@@ -510,7 +510,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
trigger(Event:L2_Replacement,
l2_victim_addr,
getL2CacheEntry(l2_victim_addr),
- TBEs[l2_victim_addr]);
+ TBEs.lookup(l2_victim_addr));
}
}
@@ -534,14 +534,14 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
trigger(Event:L1_to_L2,
l1d_victim_addr,
getL1DCacheEntry(l1d_victim_addr),
- TBEs[l1d_victim_addr]);
+ TBEs.lookup(l1d_victim_addr));
} else {
Addr l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr);
// The L2 does not have room, so we replace a line from the L2
trigger(Event:L2_Replacement,
l2_victim_addr,
getL2CacheEntry(l2_victim_addr),
- TBEs[l2_victim_addr]);
+ TBEs.lookup(l2_victim_addr));
}
}
}
@@ -926,7 +926,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
check_allocate(TBEs);
assert(is_valid(cache_entry));
TBEs.allocate(address);
- set_tbe(TBEs[address]);
+ set_tbe(TBEs.lookup(address));
tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
tbe.Dirty := cache_entry.Dirty;
tbe.Sharers := false;
@@ -935,7 +935,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
action(it_allocateTBE, "it", desc="Allocate TBE") {
check_allocate(TBEs);
TBEs.allocate(address);
- set_tbe(TBEs[address]);
+ set_tbe(TBEs.lookup(address));
tbe.Dirty := false;
tbe.Sharers := false;
}