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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:23 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:23 -0800 |
| commit | 66279fac3f099af78e63b5b181ddbd00a8b8244c (patch) | |
| tree | da0b009f4610f9e91bc1ee1c7b67bf5626595188 /src/mem/protocol/MOESI_hammer-cache.sm | |
| parent | 45230a4f6b82af61c05fcf93b6e1a9319fcb0a2e (diff) | |
| download | gem5-66279fac3f099af78e63b5b181ddbd00a8b8244c.tar.xz | |
ruby: Added atomic support to MOESI_hammer
Diffstat (limited to 'src/mem/protocol/MOESI_hammer-cache.sm')
| -rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 0efca93ae..66bb85cf9 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -245,7 +245,7 @@ machine(L1Cache, "AMD Hammer-like protocol") // Forward Network in_port(forwardToCache_in, RequestMsg, forwardToCache) { if (forwardToCache_in.isReady()) { - peek(forwardToCache_in, RequestMsg) { + peek(forwardToCache_in, RequestMsg, block_on="Address") { if (in_msg.Type == CoherenceRequestType:GETX) { trigger(Event:Other_GETX, in_msg.Address); } else if (in_msg.Type == CoherenceRequestType:GETS) { @@ -264,7 +264,7 @@ machine(L1Cache, "AMD Hammer-like protocol") // Response Network in_port(responseToCache_in, ResponseMsg, responseToCache) { if (responseToCache_in.isReady()) { - peek(responseToCache_in, ResponseMsg) { + peek(responseToCache_in, ResponseMsg, block_on="Address") { if (in_msg.Type == CoherenceResponseType:ACK) { trigger(Event:Ack, in_msg.Address); } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) { @@ -287,7 +287,7 @@ machine(L1Cache, "AMD Hammer-like protocol") // Mandatory Queue in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache |