ruby: restrict Address to being a type and not a variable name

Change all occurrances of Address as a variable name to instead use Addr.
Address is an allowed name in slicc even when Address is also being used as a
type, leading to declarations of "Address Address". While this works, it
prevents adding another field of type Address because the compiler then thinks
Address is a variable name, not type.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

1 files changed, 65 insertions, 65 deletions

diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index e1ed2feef..fc9eaa06f 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -305,19 +305,19 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=5) {
     if (triggerQueue_in.isReady()) {
       peek(triggerQueue_in, TriggerMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == TriggerType:ALL_ACKS) {
-          trigger(Event:All_acks_and_owner_data, in_msg.Address,
+          trigger(Event:All_acks_and_owner_data, in_msg.Addr,
                   pf_entry, tbe);
         } else if (in_msg.Type == TriggerType:ALL_ACKS_OWNER_EXISTS) {
-          trigger(Event:All_acks_and_shared_data, in_msg.Address,
+          trigger(Event:All_acks_and_shared_data, in_msg.Addr,
                   pf_entry, tbe);
         } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
-          trigger(Event:All_acks_and_data_no_sharers, in_msg.Address,
+          trigger(Event:All_acks_and_data_no_sharers, in_msg.Addr,
                   pf_entry, tbe);
         } else if (in_msg.Type == TriggerType:ALL_UNBLOCKS) {
-          trigger(Event:All_Unblocks, in_msg.Address,
+          trigger(Event:All_Unblocks, in_msg.Addr,
                   pf_entry, tbe);
         } else {
           error("Unexpected message");
@@ -329,23 +329,23 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(unblockNetwork_in, ResponseMsg, unblockToDir, rank=4) {
     if (unblockNetwork_in.isReady()) {
       peek(unblockNetwork_in, ResponseMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
-          trigger(Event:Unblock, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Unblock, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:UNBLOCKS) {
-          trigger(Event:UnblockS, in_msg.Address, pf_entry, tbe);
+          trigger(Event:UnblockS, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:UNBLOCKM) {
-          trigger(Event:UnblockM, in_msg.Address, pf_entry, tbe);
+          trigger(Event:UnblockM, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:WB_CLEAN) {
-          trigger(Event:Writeback_Clean, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Writeback_Clean, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:WB_DIRTY) {
-          trigger(Event:Writeback_Dirty, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Writeback_Dirty, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:WB_EXCLUSIVE_CLEAN) {
-          trigger(Event:Writeback_Exclusive_Clean, in_msg.Address,
+          trigger(Event:Writeback_Exclusive_Clean, in_msg.Addr,
                   pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:WB_EXCLUSIVE_DIRTY) {
-          trigger(Event:Writeback_Exclusive_Dirty, in_msg.Address,
+          trigger(Event:Writeback_Exclusive_Dirty, in_msg.Addr,
                   pf_entry, tbe);
         } else {
           error("Invalid message");
@@ -358,18 +358,18 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(responseToDir_in, ResponseMsg, responseToDir, rank=3) {
     if (responseToDir_in.isReady()) {
       peek(responseToDir_in, ResponseMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:Ack, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Ack, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
-          trigger(Event:Shared_Ack, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Shared_Ack, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
-          trigger(Event:Shared_Data, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Shared_Data, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Data, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
-          trigger(Event:Exclusive_Data, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Exclusive_Data, in_msg.Addr, pf_entry, tbe);
         } else {
           error("Unexpected message");
         }
@@ -381,12 +381,12 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(memQueue_in, MemoryMsg, memBuffer, rank=2) {
     if (memQueue_in.isReady()) {
       peek(memQueue_in, MemoryMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
-          trigger(Event:Memory_Data, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Memory_Data, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
-          trigger(Event:Memory_Ack, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Memory_Ack, in_msg.Addr, pf_entry, tbe);
         } else {
           DPRINTF(RubySlicc, "%d\n", in_msg.Type);
           error("Invalid message");
@@ -398,30 +398,30 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) {
     if (requestQueue_in.isReady()) {
       peek(requestQueue_in, RequestMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == CoherenceRequestType:PUT) {
-          trigger(Event:PUT, in_msg.Address, pf_entry, tbe);
+          trigger(Event:PUT, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:PUTF) {
-          trigger(Event:PUTF, in_msg.Address, pf_entry, tbe);
+          trigger(Event:PUTF, in_msg.Addr, pf_entry, tbe);
         } else {
           if (probe_filter_enabled || full_bit_dir_enabled) {
             if (is_valid(pf_entry)) {
-              trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
+              trigger(cache_request_to_event(in_msg.Type), in_msg.Addr,
                       pf_entry, tbe);
             } else {
-              if (probeFilter.cacheAvail(in_msg.Address)) {
-                trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
+              if (probeFilter.cacheAvail(in_msg.Addr)) {
+                trigger(cache_request_to_event(in_msg.Type), in_msg.Addr,
                         pf_entry, tbe);
               } else {
                 trigger(Event:Pf_Replacement,
-                        probeFilter.cacheProbe(in_msg.Address),
-                        getProbeFilterEntry(probeFilter.cacheProbe(in_msg.Address)),
-                        TBEs[probeFilter.cacheProbe(in_msg.Address)]);
+                        probeFilter.cacheProbe(in_msg.Addr),
+                        getProbeFilterEntry(probeFilter.cacheProbe(in_msg.Addr)),
+                        TBEs[probeFilter.cacheProbe(in_msg.Addr)]);
               }
             }
           } else {
-            trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
+            trigger(cache_request_to_event(in_msg.Type), in_msg.Addr,
                     pf_entry, tbe);
           }
         }
@@ -493,7 +493,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_ACK;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination.add(in_msg.Requestor);
@@ -506,7 +506,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(requestQueue_in, RequestMsg) {
         if (((probe_filter_enabled || full_bit_dir_enabled) && (in_msg.Requestor == cache_entry.Owner)) || machineCount(MachineType:L1Cache) == 1) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:BLOCK_ACK;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.Destination.add(in_msg.Requestor);
@@ -519,7 +519,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_NACK;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination.add(in_msg.Requestor);
@@ -678,7 +678,7 @@ machine(Directory, "AMD Hammer-like protocol")
     assert(is_valid(tbe));
     if (tbe.NumPendingMsgs == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         if (tbe.Sharers) {
           if (tbe.Owned) {
             out_msg.Type := TriggerType:ALL_ACKS_OWNER_EXISTS;
@@ -696,7 +696,7 @@ machine(Directory, "AMD Hammer-like protocol")
     assert(is_valid(tbe));
     if (tbe.NumPendingMsgs == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := TriggerType:ALL_UNBLOCKS;
       }
     }
@@ -719,7 +719,7 @@ machine(Directory, "AMD Hammer-like protocol")
     if (tbe.NumPendingMsgs == 0) {
       assert(probe_filter_enabled || full_bit_dir_enabled);
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
       }
     }
@@ -729,7 +729,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := tbe.ResponseType;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
@@ -837,7 +837,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
@@ -851,7 +851,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(qd_queueMemoryRequestFromDmaRead, "qd", desc="Queue off-chip fetch request") {
     peek(dmaRequestQueue_in, DMARequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
@@ -872,7 +872,7 @@ machine(Directory, "AMD Hammer-like protocol")
           fwd_set.remove(machineIDToNodeID(in_msg.Requestor));
           if (fwd_set.count() > 0) {
             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-              out_msg.Address := address;
+              out_msg.Addr := address;
               out_msg.Type := in_msg.Type;
               out_msg.Requestor := in_msg.Requestor;
               out_msg.Destination.setNetDest(MachineType:L1Cache, fwd_set);
@@ -887,7 +887,7 @@ machine(Directory, "AMD Hammer-like protocol")
       } else {
         peek(requestQueue_in, RequestMsg) {
           enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := in_msg.Type;
             out_msg.Requestor := in_msg.Requestor;
             out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -907,7 +907,7 @@ machine(Directory, "AMD Hammer-like protocol")
         assert(cache_entry.Sharers.count() > 0);
         peek(requestQueue_in, RequestMsg) {
           enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := CoherenceRequestType:INV;
             out_msg.Requestor := machineID;
             out_msg.Destination.setNetDest(MachineType:L1Cache, cache_entry.Sharers);
@@ -916,7 +916,7 @@ machine(Directory, "AMD Hammer-like protocol")
         }
       } else {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:INV;
           out_msg.Requestor := machineID;
           out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -930,7 +930,7 @@ machine(Directory, "AMD Hammer-like protocol")
     if (machineCount(MachineType:L1Cache) > 1) {
       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
         assert(is_valid(cache_entry)); 
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := machineID;
         out_msg.Destination.add(cache_entry.Owner);
@@ -948,7 +948,7 @@ machine(Directory, "AMD Hammer-like protocol")
           fwd_set.remove(machineIDToNodeID(in_msg.Requestor));
           if (fwd_set.count() > 0) {
             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-                  out_msg.Address := address;
+                  out_msg.Addr := address;
                   out_msg.Type := in_msg.Type;
                   out_msg.Requestor := in_msg.Requestor;
                   out_msg.Destination.setNetDest(MachineType:L1Cache, fwd_set);
@@ -961,7 +961,7 @@ machine(Directory, "AMD Hammer-like protocol")
           }
         } else {
             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-                out_msg.Address := address;
+                out_msg.Addr := address;
                 out_msg.Type := in_msg.Type;
                 out_msg.Requestor := in_msg.Requestor;
                 out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -975,7 +975,7 @@ machine(Directory, "AMD Hammer-like protocol")
     } else {
       peek(requestQueue_in, RequestMsg) {
           enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := CoherenceResponseType:ACK;
             out_msg.Sender := machineID;
             out_msg.Destination.add(in_msg.Requestor);
@@ -998,7 +998,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(unblockNetwork_in, ResponseMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:MERGED_GETS;
         out_msg.MergedRequestors := tbe.GetSRequestors;
         if (in_msg.Type == CoherenceResponseType:UNBLOCKS) {
@@ -1019,7 +1019,7 @@ machine(Directory, "AMD Hammer-like protocol")
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
           assert(is_valid(cache_entry)); 
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := in_msg.Type;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.Destination.add(cache_entry.Owner);
@@ -1032,7 +1032,7 @@ machine(Directory, "AMD Hammer-like protocol")
     } else {
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := in_msg.Type;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -1053,7 +1053,7 @@ machine(Directory, "AMD Hammer-like protocol")
         if (in_msg.Requestor != cache_entry.Owner) {
           enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
             assert(is_valid(cache_entry));
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := in_msg.Type;
             out_msg.Requestor := in_msg.Requestor;
             out_msg.Destination.add(cache_entry.Owner);
@@ -1067,7 +1067,7 @@ machine(Directory, "AMD Hammer-like protocol")
      } else {
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := in_msg.Type;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -1086,7 +1086,7 @@ machine(Directory, "AMD Hammer-like protocol")
     if (tbe.NumPendingMsgs > 0) {
       peek(dmaRequestQueue_in, DMARequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:GETX;
           //
           // Send to all L1 caches, since the requestor is the memory controller
@@ -1105,7 +1105,7 @@ machine(Directory, "AMD Hammer-like protocol")
     if (tbe.NumPendingMsgs > 0) {
       peek(dmaRequestQueue_in, DMARequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:GETS;
           //
           // Send to all L1 caches, since the requestor is the memory controller
@@ -1174,7 +1174,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(responseToDir_in, ResponseMsg) {
       getDirectoryEntry(address).DataBlk := in_msg.DataBlk;
       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
-              in_msg.Address, in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk);
     }
   }
 
@@ -1182,7 +1182,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(memQueue_in, MemoryMsg) {
       getDirectoryEntry(address).DataBlk := in_msg.DataBlk;
       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
-              in_msg.Address, in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk);
     }
   }
 
@@ -1247,7 +1247,7 @@ machine(Directory, "AMD Hammer-like protocol")
       enqueue(memQueue_out, MemoryMsg, latency="1") {
         assert(in_msg.Dirty);
         assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.DataBlk := in_msg.DataBlk;
         DPRINTF(RubySlicc, "%s\n", out_msg);
@@ -1258,7 +1258,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(ld_queueMemoryDmaWrite, "ld", desc="Write DMA data to memory") {
     enqueue(memQueue_out, MemoryMsg, latency="1") {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := MemoryRequestType:MEMORY_WB;
       // first, initialize the data blk to the current version of system memory
       out_msg.DataBlk := tbe.DataBlk;