Merge Ruby Stuff

1 files changed, 62 insertions, 0 deletions

diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm
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index 000000000..0c205ac22
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+++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm
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+
+/*
+ * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// Mapping functions
+
+// NodeID map_address_to_node(Address addr);
+MachineID map_Address_to_Directory(Address addr);
+NodeID map_Address_to_DirectoryNode(Address addr);
+MachineID map_Address_to_CentralArbiterNode(Address addr);
+NodeID oldmap_L1RubyNode_to_L2Cache(Address addr, NodeID L1RubyNode);
+MachineID map_L1CacheMachId_to_L2Cache(Address addr, MachineID L1CacheMachId);
+MachineID map_L2ChipId_to_L2Cache(Address addr, NodeID L2ChipId);
+// MachineID map_L1RubyNode_to_Arb(NodeID L1RubyNode);
+
+MachineID getL1MachineID(NodeID L1RubyNode);
+NodeID getChipID(MachineID L2machID);
+MachineID getCollectorDest(MachineID L1machID);
+MachineID getCollectorL1Cache(MachineID colID);
+NetDest getMultiStaticL2BankNetDest(Address addr, Set sharers);
+bool isL1OnChip(MachineID L1machID, NodeID L2NodeID);
+bool isL2OnChip(MachineID L2machID, NodeID L2NodeID);
+
+int getNumBanksInBankSet();
+NodeID machineIDToNodeID(MachineID machID);
+NodeID machineIDToVersion(MachineID machID);
+MachineType machineIDToMachineType(MachineID machID);
+NodeID L1CacheMachIDToProcessorNum(MachineID machID);
+NodeID L2CacheMachIDToChipID(MachineID machID);
+Set getOtherLocalL1IDs(MachineID L1);
+Set getLocalL1IDs(MachineID L1);
+Set getExternalL1IDs(MachineID L1);
+NetDest getAllPertinentL2Banks(Address addr);
+bool isLocalProcessor(MachineID thisId, MachineID tarId);
+
+GenericMachineType ConvertMachToGenericMach(MachineType machType);
+