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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-04 00:03:34 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-04 00:03:34 -0600 |
| commit | 4070b00875a5fcc3cde61ff0b32fbee882998189 (patch) | |
| tree | 245f49626f3abf0c378397025638adc7afaee9b5 /src/mem/protocol/RubySlicc_ComponentMapping.sm | |
| parent | bb6d7d402b5cc610ed879e9e7ecb251e353149e6 (diff) | |
| download | gem5-4070b00875a5fcc3cde61ff0b32fbee882998189.tar.xz | |
ruby: add a three level MESI protocol.
The first two levels (L0, L1) are private to the core, the third level (L2)is
possibly shared. The protocol supports clustered designs. For example, one
can have two sets of two cores. Each core has an L0 and L1 cache. There are
two L2 controllers where each set accesses only one of the L2 controllers.
Diffstat (limited to 'src/mem/protocol/RubySlicc_ComponentMapping.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_ComponentMapping.sm | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm index 4744c9d4f..37b2c3ef4 100644 --- a/src/mem/protocol/RubySlicc_ComponentMapping.sm +++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm @@ -39,3 +39,4 @@ NodeID map_Address_to_DirectoryNode(Address addr); NodeID machineIDToNodeID(MachineID machID); NodeID machineIDToVersion(MachineID machID); MachineType machineIDToMachineType(MachineID machID); +MachineID createMachineID(MachineType t, NodeID i); |