diff options
author | Derek Hower <drh5@cs.wisc.edu> | 2009-08-04 12:52:52 -0500 |
---|---|---|
committer | Derek Hower <drh5@cs.wisc.edu> | 2009-08-04 12:52:52 -0500 |
commit | 33b28fde7aca9bf1ae16b9db09e71ccd44d3ae76 (patch) | |
tree | fe2a4aee5517aed63f95e56ce4f085793826bdd4 /src/mem/protocol/RubySlicc_ComponentMapping.sm | |
parent | c1e0bd1df4cf107bd543bcde9c9ab7be41d6dce3 (diff) | |
download | gem5-33b28fde7aca9bf1ae16b9db09e71ccd44d3ae76.tar.xz |
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers
This changeset contains a lot of different changes that are too
mingled to separate. They are:
1. Added MOESI_CMP_directory
I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.
2. DMA Sequencer uses a generic SequencerMsg
I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.
3. Parameterized Controllers
SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.
Diffstat (limited to 'src/mem/protocol/RubySlicc_ComponentMapping.sm')
-rw-r--r-- | src/mem/protocol/RubySlicc_ComponentMapping.sm | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm index 022bb6862..559e54a8c 100644 --- a/src/mem/protocol/RubySlicc_ComponentMapping.sm +++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm @@ -30,14 +30,11 @@ // Mapping functions // NodeID map_address_to_node(Address addr); +MachineID mapAddressToRange(Address addr, MachineType type, int low, int high); MachineID map_Address_to_DMA(Address addr); MachineID map_Address_to_Directory(Address addr); NodeID map_Address_to_DirectoryNode(Address addr); -MachineID map_Address_to_CentralArbiterNode(Address addr); -NodeID oldmap_L1RubyNode_to_L2Cache(Address addr, NodeID L1RubyNode); -MachineID map_L1CacheMachId_to_L2Cache(Address addr, MachineID L1CacheMachId); -MachineID map_L2ChipId_to_L2Cache(Address addr, NodeID L2ChipId); -// MachineID map_L1RubyNode_to_Arb(NodeID L1RubyNode); + MachineID getL1MachineID(NodeID L1RubyNode); NodeID getChipID(MachineID L2machID); |