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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-04 00:03:34 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-04 00:03:34 -0600 |
| commit | 4070b00875a5fcc3cde61ff0b32fbee882998189 (patch) | |
| tree | 245f49626f3abf0c378397025638adc7afaee9b5 /src/mem/protocol/RubySlicc_Defines.sm | |
| parent | bb6d7d402b5cc610ed879e9e7ecb251e353149e6 (diff) | |
| download | gem5-4070b00875a5fcc3cde61ff0b32fbee882998189.tar.xz | |
ruby: add a three level MESI protocol.
The first two levels (L0, L1) are private to the core, the third level (L2)is
possibly shared. The protocol supports clustered designs. For example, one
can have two sets of two cores. Each core has an L0 and L1 cache. There are
two L2 controllers where each set accesses only one of the L2 controllers.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Defines.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Defines.sm | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/protocol/RubySlicc_Defines.sm index f3923eb9f..1480790bf 100644 --- a/src/mem/protocol/RubySlicc_Defines.sm +++ b/src/mem/protocol/RubySlicc_Defines.sm @@ -28,7 +28,6 @@ */ // Hack, no node object since base class has them -NodeID id; NodeID version; MachineID machineID; NodeID clusterID; |