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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:50:11 +0800 |
| commit | a4c6e88d766858b675a7fd256df5a8b9a7e18ada (patch) | |
| tree | a00f59eea3e87c31eb9efbce9f8d6f397ae16db2 /src/mem/protocol/RubySlicc_Defines.sm | |
| parent | 866b200c202dded37fdd857a1a42ec149bd109c9 (diff) | |
| download | gem5-a4c6e88d766858b675a7fd256df5a8b9a7e18ada.tar.xz | |
import invisispec-1.0 source by Mengjia Yan
The original code is at https://github.com/mjyan0720/InvisiSpec-1.0
This code is rebased on upstream gem5 commit 866b200c, which features:
- rdtscp support
- some C++ code optimizations
- newer Linux kernel version number in SE mode
Diffstat (limited to 'src/mem/protocol/RubySlicc_Defines.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Defines.sm | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/protocol/RubySlicc_Defines.sm index eb235f8f3..7df82847e 100644 --- a/src/mem/protocol/RubySlicc_Defines.sm +++ b/src/mem/protocol/RubySlicc_Defines.sm @@ -35,7 +35,7 @@ Cycles recycle_latency; // Functions implemented in the AbstractController class for // making timing access to the memory maintained by the // memory controllers. -void queueMemoryRead(MachineID id, Addr addr, Cycles latency); +void queueMemoryRead(MachineID id, Addr addr, Cycles latency, MachineID origin, int idx, int type); void queueMemoryWrite(MachineID id, Addr addr, Cycles latency, DataBlock block); void queueMemoryWritePartial(MachineID id, Addr addr, Cycles latency, |