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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:51 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:51 -0500 |
commit | 91a84c5b3cfb888794ac0245c066a4724b9a0871 (patch) | |
tree | 79a8b41aff56655dbd187934d2709fdd7488c6ed /src/mem/protocol/RubySlicc_Defines.sm | |
parent | 9ea5d9cad9381e05004de28ef25309ebe94c3a79 (diff) | |
download | gem5-91a84c5b3cfb888794ac0245c066a4724b9a0871.tar.xz |
ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Defines.sm')
-rw-r--r-- | src/mem/protocol/RubySlicc_Defines.sm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/protocol/RubySlicc_Defines.sm index d25250864..d4f7fa58f 100644 --- a/src/mem/protocol/RubySlicc_Defines.sm +++ b/src/mem/protocol/RubySlicc_Defines.sm @@ -35,10 +35,10 @@ NodeID clusterID; // Functions implemented in the AbstractController class for // making timing access to the memory maintained by the // memory controllers. -void queueMemoryRead(MachineID id, Address addr, Cycles latency); -void queueMemoryWrite(MachineID id, Address addr, Cycles latency, +void queueMemoryRead(MachineID id, Addr addr, Cycles latency); +void queueMemoryWrite(MachineID id, Addr addr, Cycles latency, DataBlock block); -void queueMemoryWritePartial(MachineID id, Address addr, Cycles latency, +void queueMemoryWritePartial(MachineID id, Addr addr, Cycles latency, DataBlock block, int size); // Functions implemented in the AbstractController class for |