diff options
| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-11 13:34:03 +0800 |
| commit | 156b2eaa59f063e53e3fa9ea82632821f999352e (patch) | |
| tree | 8fba561f7e4402271bd86afe6e0d21276bbf022e /src/mem/protocol/RubySlicc_Defines.sm | |
| parent | f1b7d0afe93497ef55e857cdd7ae9e168970bd65 (diff) | |
| download | gem5-156b2eaa59f063e53e3fa9ea82632821f999352e.tar.xz | |
invisispec-1.0 source
Diffstat (limited to 'src/mem/protocol/RubySlicc_Defines.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Defines.sm | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/protocol/RubySlicc_Defines.sm index eb235f8f3..7df82847e 100644 --- a/src/mem/protocol/RubySlicc_Defines.sm +++ b/src/mem/protocol/RubySlicc_Defines.sm @@ -35,7 +35,7 @@ Cycles recycle_latency; // Functions implemented in the AbstractController class for // making timing access to the memory maintained by the // memory controllers. -void queueMemoryRead(MachineID id, Addr addr, Cycles latency); +void queueMemoryRead(MachineID id, Addr addr, Cycles latency, MachineID origin, int idx, int type); void queueMemoryWrite(MachineID id, Addr addr, Cycles latency, DataBlock block); void queueMemoryWritePartial(MachineID id, Addr addr, Cycles latency, |