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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 14:32:29 +0800 |
| commit | a17658beaacabe018be78c32aafe8415cdb16df0 (patch) | |
| tree | 0432a6af261efd0ef03c318a67cf880a7461cc5d /src/mem/protocol/RubySlicc_Defines.sm | |
| parent | 59505f7305cc3f3b7637233fd2d231bd7f561e80 (diff) | |
| download | gem5-a17658beaacabe018be78c32aafe8415cdb16df0.tar.xz | |
invisispec-1.0 source
Diffstat (limited to 'src/mem/protocol/RubySlicc_Defines.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Defines.sm | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/protocol/RubySlicc_Defines.sm index eb235f8f3..7df82847e 100644 --- a/src/mem/protocol/RubySlicc_Defines.sm +++ b/src/mem/protocol/RubySlicc_Defines.sm @@ -35,7 +35,7 @@ Cycles recycle_latency; // Functions implemented in the AbstractController class for // making timing access to the memory maintained by the // memory controllers. -void queueMemoryRead(MachineID id, Addr addr, Cycles latency); +void queueMemoryRead(MachineID id, Addr addr, Cycles latency, MachineID origin, int idx, int type); void queueMemoryWrite(MachineID id, Addr addr, Cycles latency, DataBlock block); void queueMemoryWritePartial(MachineID id, Addr addr, Cycles latency, |