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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:07:04 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:07:04 -0400
commit36d199b9a96838359230f1ae8a40446e05296145 (patch)
tree8d96e6243c2693fc290b0841477b30300a1f3245 /src/mem/protocol/RubySlicc_Exports.sm
parent43ca8415e8747145cb1a410d4672d4cd2247c695 (diff)
downloadgem5-36d199b9a96838359230f1ae8a40446e05296145.tar.xz
Mem: Use range operations in bus in preparation for striping
This patch transitions the bus to use the AddrRange operations instead of directly accessing the start and end. The change facilitates the move to a more elaborate AddrRange class that also supports address striping in the bus by specifying interleaving bits in the ranges. Two new functions are added to the AddrRange to determine if two ranges intersect, and if one is a subset of another. The bus propagation of address ranges is also tweaked such that an update is only propagated if the bus received information from all the downstream slave modules. This avoids the iteration and need for the cycle-breaking scheme that was previously used.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Exports.sm')
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