ruby: profiler: lots of inter-related changes

The patch started of with removing the global variables from the profiler for
profiling the miss latency of requests made to the cache. The corrresponding
histograms have been moved to the Sequencer. These are combined together when
the histograms are printed. Separate histograms are now maintained for
tracking latency of all requests together, of hits only and of misses only.

A particular set of histograms used to use the type GenericMachineType defined
in one of the protocol files. This patch removes this type. Now, everything
that relied on this type would use MachineType instead. To do this, SLICC has
been changed so that multiple machine types can be declared by a controller
in its preamble.

1 files changed, 0 insertions, 12 deletions

diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index 015ae8cb3..e0371f896 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -168,18 +168,6 @@ enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestT
   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 }
 
-enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
-  L1Cache,     desc="L1 Cache Mach";
-  L2Cache,     desc="L2 Cache Mach";
-  L3Cache,     desc="L3 Cache Mach";
-  Directory,   desc="Directory Mach";
-  DMA,         desc="DMA Mach";
-  Collector,   desc="Collector Mach";
-  L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
-  L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
-  NULL,        desc="null mach type";
-}
-
 // MessageSizeType
 enumeration(MessageSizeType, default="MessageSizeType_Undefined", desc="...") {
   Undefined,  desc="Undefined";