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authorNilay Vaish <nilay@cs.wisc.edu>2011-03-19 18:34:37 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2011-03-19 18:34:37 -0500
commit2f4276448b82b2aa077ae257171b5cb04b7048f6 (patch)
tree7e5d6bdcf8b3028ac7aed6c889efb820b2db91d9 /src/mem/protocol/RubySlicc_Exports.sm
parentdd9083115ed3f1ee297c2ff7255fdd3fee276e7a (diff)
downloadgem5-2f4276448b82b2aa077ae257171b5cb04b7048f6.tar.xz
Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the protocol dependent and independent code uses the same access mode.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Exports.sm')
-rw-r--r--src/mem/protocol/RubySlicc_Exports.sm13
1 files changed, 7 insertions, 6 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index e3eb8ebeb..7258e9ccd 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -193,10 +193,11 @@ enumeration(AccessType, desc="...") {
Write, desc="Writing to cache";
}
-// AccessModeType
-enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") {
- SupervisorMode, desc="Supervisor mode";
- UserMode, desc="User mode";
+// RubyAccessMode
+enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
+ Supervisor, desc="Supervisor mode";
+ User, desc="User mode";
+ Device, desc="Device mode";
}
enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
@@ -212,7 +213,7 @@ structure(CacheMsg, desc="...", interface="Message") {
Address PhysicalAddress, desc="Physical address for this request";
CacheRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
@@ -223,7 +224,7 @@ structure(SequencerMsg, desc="...", interface="Message") {
Address PhysicalAddress, desc="Physical address for this request";
SequencerRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
DataBlock DataBlk, desc="Data";
int Len, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";