slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate.  They are:

1.  Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller.  I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2.  DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well.  It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc.  Currently, only int parameters are supported.

1 files changed, 25 insertions, 8 deletions

diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index a8b58b96c..412fd0de0 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -39,7 +39,10 @@ external_type(string, primitive="yes");
 external_type(uint64, primitive="yes");
 external_type(Time, primitive="yes", default="0");
 external_type(Address);
-
+external_type(DataBlock, desc="..."){
+  void clear();
+  void copyPartial(DataBlock, int, int);
+}
 
 // Declarations of external types that are common to all protocols
 
@@ -131,12 +134,12 @@ enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
   IO,          desc="I/O";
   REPLACEMENT, desc="Replacement";
   COMMIT,      desc="Commit version";
-  LD_XACT,     desc="Transactional Load";
-  LDX_XACT,    desc="Transactional Load-Intend-To-Modify";
-  ST_XACT,     desc="Transactional Store";
-  BEGIN_XACT,  desc="Begin Transaction";
-  COMMIT_XACT, desc="Commit Transaction";
-  ABORT_XACT,  desc="Abort Transaction";
+  NULL,        desc="Invalid request type";
+}
+
+enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
+  LD,          desc="Load";
+  ST,          desc="Store";
   NULL,        desc="Invalid request type";
 }
 
@@ -167,7 +170,9 @@ enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") {
   ST_XACT,     desc="Transactional Store";
   BEGIN_XACT,  desc="Begin Transaction";
   COMMIT_XACT, desc="Commit Transaction";
-  ABORT_XACT,  desc="Abort Transaction";
+  ABORT_XACT,  desc="Abort Transaction";	
+  DMA_READ,    desc="DMA READ";
+  DMA_WRITE,   desc="DMA WRITE";
   NULL,        desc="null request type";
 }
 
@@ -232,6 +237,18 @@ structure(CacheMsg, desc="...", interface="Message") {
   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 }
 
+// CacheMsg
+structure(SequencerMsg, desc="...", interface="Message") {
+  Address LineAddress,       desc="Line address for this request";
+  Address PhysicalAddress,   desc="Physical address for this request";
+  SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
+  Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
+  AccessModeType AccessMode, desc="user/supervisor access type";
+  DataBlock DataBlk,         desc="Data";
+  int Len,                   desc="size in bytes of access";
+  PrefetchBit Prefetch,      desc="Is this a prefetch request";
+}
+
 // MaskPredictorType
 enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
   Undefined, desc="Undefined";