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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2011-03-19 18:34:59 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2011-03-19 18:34:59 -0500 |
| commit | 611f052e963b06b4a7e02b2fc6d847cd6d08d038 (patch) | |
| tree | 0a3bdb5787d5e6ae9b0e07145cf2d32b4a532d6b /src/mem/protocol/RubySlicc_Exports.sm | |
| parent | 2f4276448b82b2aa077ae257171b5cb04b7048f6 (diff) | |
| download | gem5-611f052e963b06b4a7e02b2fc6d847cd6d08d038.tar.xz | |
Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Exports.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Exports.sm | 28 |
1 files changed, 17 insertions, 11 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 7258e9ccd..1f7a1dda2 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -103,16 +103,22 @@ enumeration(TransitionResult, desc="...") { ProtocolStall, desc="Protocol specified stall"; } -// CacheRequestType -enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") { - LD, desc="Load"; - ST, desc="Store"; - ATOMIC, desc="Atomic Load/Store"; - IFETCH, desc="Instruction fetch"; - IO, desc="I/O"; - REPLACEMENT, desc="Replacement"; - COMMIT, desc="Commit version"; - NULL, desc="Invalid request type"; +// RubyRequestType +enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") { + LD, desc="Load"; + ST, desc="Store"; + ATOMIC, desc="Atomic Load/Store"; + IFETCH, desc="Instruction fetch"; + IO, desc="I/O"; + REPLACEMENT, desc="Replacement"; + Load_Linked, desc=""; + Store_Conditional, desc=""; + RMW_Read, desc=""; + RMW_Write, desc=""; + Locked_RMW_Read, desc=""; + Locked_RMW_Write, desc=""; + COMMIT, desc="Commit version"; + NULL, desc="Invalid request type"; } enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") { @@ -211,7 +217,7 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") { structure(CacheMsg, desc="...", interface="Message") { Address LineAddress, desc="Line address for this request"; Address PhysicalAddress, desc="Physical address for this request"; - CacheRequestType Type, desc="Type of request (LD, ST, etc)"; + RubyRequestType Type, desc="Type of request (LD, ST, etc)"; Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; RubyAccessMode AccessMode, desc="user/supervisor access type"; int Size, desc="size in bytes of access"; |