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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-07-10 22:51:54 -0700 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-07-10 22:51:54 -0700 |
commit | 86d6b788f6d7b523c750ffb64d6d8920ec741c49 (patch) | |
tree | 2d6be00e66218b39bae31a27380a47283f70c097 /src/mem/protocol/RubySlicc_Exports.sm | |
parent | 467093ebf238a1954e00576daf14a9f246b51e79 (diff) | |
download | gem5-86d6b788f6d7b523c750ffb64d6d8920ec741c49.tar.xz |
ruby: banked cache array resource model
This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Exports.sm')
-rw-r--r-- | src/mem/protocol/RubySlicc_Exports.sm | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index ef752c604..92739385b 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -184,6 +184,11 @@ enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") { TagArrayWrite, desc="Write access to the cache's tag array"; } +enumeration(CacheResourceType, desc="...", default="CacheResourceType_NULL") { + DataArray, desc="Access to the cache's data array"; + TagArray, desc="Access to the cache's tag array"; +} + enumeration(DirectoryRequestType, desc="...", default="DirectoryRequestType_NULL") { Default, desc="Replace this with access_types passed to the Directory Ruby object"; } |