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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:51 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:51 -0500 |
commit | 91a84c5b3cfb888794ac0245c066a4724b9a0871 (patch) | |
tree | 79a8b41aff56655dbd187934d2709fdd7488c6ed /src/mem/protocol/RubySlicc_Exports.sm | |
parent | 9ea5d9cad9381e05004de28ef25309ebe94c3a79 (diff) | |
download | gem5-91a84c5b3cfb888794ac0245c066a4724b9a0871.tar.xz |
ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Exports.sm')
-rw-r--r-- | src/mem/protocol/RubySlicc_Exports.sm | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 1d591482d..b643a3da1 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -35,7 +35,7 @@ external_type(uint32_t, primitive="yes"); external_type(uint64, primitive="yes"); external_type(PacketPtr, primitive="yes"); external_type(Packet, primitive="yes"); -external_type(Address); +external_type(Addr, primitive="yes"); external_type(Cycles, primitive="yes", default="Cycles(0)"); structure(DataBlock, external = "yes", desc="..."){ @@ -43,8 +43,8 @@ structure(DataBlock, external = "yes", desc="..."){ void copyPartial(DataBlock, int, int); } -bool testAndRead(Address addr, DataBlock datablk, Packet *pkt); -bool testAndWrite(Address addr, DataBlock datablk, Packet *pkt); +bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt); +bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt); // AccessPermission // The following five states define the access permission of all memory blocks. @@ -215,10 +215,10 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") { // CacheMsg structure(SequencerMsg, desc="...", interface="Message") { - Address LineAddress, desc="Line address for this request"; - Address PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; SequencerRequestType Type, desc="Type of request (LD, ST, etc)"; - Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; + Addr ProgramCounter, desc="Program counter of the instruction that caused the miss"; RubyAccessMode AccessMode, desc="user/supervisor access type"; DataBlock DataBlk, desc="Data"; int Len, desc="size in bytes of access"; |