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authorTony Gutierrez <anthony.gutierrez@amd.com>2015-07-20 09:15:18 -0500
committerTony Gutierrez <anthony.gutierrez@amd.com>2015-07-20 09:15:18 -0500
commita3177645773b8eb4b835050c395554d3e2b4664a (patch)
tree793299969de1562785063448ac12f9e06ac164e3 /src/mem/protocol/RubySlicc_Exports.sm
parent3f68884c0e432cdc241ed0442e19ade0d74aa6f4 (diff)
downloadgem5-a3177645773b8eb4b835050c395554d3e2b4664a.tar.xz
ruby: slicc: have a static MachineType
This patch is imported from reviewboard patch 2551 by Nilay. This patch moves from a dynamically defined MachineType to a statically defined one. The need for this patch was felt since a dynamically defined type prevents us from having types for which no machine definition may exist. The following changes have been made: i. each machine definition now uses a type from the MachineType enumeration instead of any random identifier. This required changing the grammar and the *.sm files. ii. MachineType enumeration defined statically in RubySlicc_Exports.sm. * * * normal protocol fixes for nilay's parser machine type fix
Diffstat (limited to 'src/mem/protocol/RubySlicc_Exports.sm')
-rw-r--r--src/mem/protocol/RubySlicc_Exports.sm18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index 7c2069203..617989d15 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -173,6 +173,24 @@ enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestT
Default, desc="Replace this with access_types passed to the DMA Ruby object";
}
+
+// These are statically defined types of states machines that we can have.
+// If you want to add a new machine type, edit this enum. It is not necessary
+// for a protocol to have state machines defined for the all types here. But
+// you cannot use anything other than the ones defined here. Also, a protocol
+// can have only one state machine for a given type.
+enumeration(MachineType, desc="...", default="MachineType_NULL") {
+ L1Cache, desc="L1 Cache Mach";
+ L2Cache, desc="L2 Cache Mach";
+ L3Cache, desc="L3 Cache Mach";
+ Directory, desc="Directory Mach";
+ DMA, desc="DMA Mach";
+ Collector, desc="Collector Mach";
+ L1Cache_wCC, desc="L1 Cache Mach to track cache-to-cache transfer (used for miss latency profile)";
+ L2Cache_wCC, desc="L2 Cache Mach to track cache-to-cache transfer (used for miss latency profile)";
+ NULL, desc="null mach type";
+}
+
// MessageSizeType
enumeration(MessageSizeType, desc="...") {
Control, desc="Control Message";