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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-07-10 22:51:54 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-07-10 22:51:54 -0700 |
| commit | 86d6b788f6d7b523c750ffb64d6d8920ec741c49 (patch) | |
| tree | 2d6be00e66218b39bae31a27380a47283f70c097 /src/mem/protocol/RubySlicc_Types.sm | |
| parent | 467093ebf238a1954e00576daf14a9f246b51e79 (diff) | |
| download | gem5-86d6b788f6d7b523c750ffb64d6d8920ec741c49.tar.xz | |
ruby: banked cache array resource model
This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Types.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Types.sm | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index 436b39273..a14af946c 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -109,6 +109,7 @@ structure (Sequencer, external = "yes") { void profileNack(Address, int, int, uint64); void evictionCallback(Address); void recordRequestType(SequencerRequestType); + bool checkResourceAvailable(CacheResourceType, Address); } structure(RubyRequest, desc="...", interface="Message", external="yes") { @@ -154,6 +155,7 @@ structure (CacheMemory, external = "yes") { void setMRU(Address); void recordRequestType(CacheRequestType); + bool checkResourceAvailable(CacheResourceType, Address); } structure (WireBuffer, inport="yes", outport="yes", external = "yes") { |