diff options
| author | Blake Hechtman <blake.hechtman@amd.com> | 2015-07-20 09:15:18 -0500 |
|---|---|---|
| committer | Blake Hechtman <blake.hechtman@amd.com> | 2015-07-20 09:15:18 -0500 |
| commit | 34fb6b5e35db751f310aee824046107e57a0ba03 (patch) | |
| tree | 4f07b86c4d50f0431a8451406026a693ccbb1e39 /src/mem/protocol/RubySlicc_Types.sm | |
| parent | b7ea2bc705bfae2e7719d6259cc14de95f4f991d (diff) | |
| download | gem5-34fb6b5e35db751f310aee824046107e57a0ba03.tar.xz | |
mem: misc flags for AMD gpu model
This patch add support to mark memory requests/packets with attributes defined
in HSA, such as memory order and scope.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Types.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Types.sm | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index 8e846098c..c7479089b 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -126,6 +126,8 @@ structure(RubyRequest, desc="...", interface="Message", external="yes") { int Size, desc="size in bytes of access"; PrefetchBit Prefetch, desc="Is this a prefetch request"; int contextId, desc="this goes away but must be replace with Nilay"; + HSAScope scope, desc="HSA scope"; + HSASegment segment, desc="HSA segment"; } structure(AbstractEntry, primitive="yes", external = "yes") { |