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authorTony Gutierrez <anthony.gutierrez@amd.com>2016-01-19 13:57:50 -0500
committerTony Gutierrez <anthony.gutierrez@amd.com>2016-01-19 13:57:50 -0500
commitd658b6e1cc22de852fef611e28f448257acc298a (patch)
tree9d4ab8f7531647eb7df619c77e8ddb2ae1022bcf /src/mem/protocol/RubySlicc_Types.sm
parent34fb6b5e35db751f310aee824046107e57a0ba03 (diff)
downloadgem5-d658b6e1cc22de852fef611e28f448257acc298a.tar.xz
* * *
mem: support for gpu-style RMWs in ruby This patch adds support for GPU-style read-modify-write (RMW) operations in ruby. Such atomic operations are traditionally executed at the memory controller (instead of through an L1 cache using cache-line locking). Currently, this patch works by propogating operation functors through the memory system.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Types.sm')
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index c7479089b..95fa1db17 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -126,6 +126,7 @@ structure(RubyRequest, desc="...", interface="Message", external="yes") {
int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
int contextId, desc="this goes away but must be replace with Nilay";
+ int wfid, desc="Writethrough wavefront";
HSAScope scope, desc="HSA scope";
HSASegment segment, desc="HSA segment";
}