ruby: slicc: change the way configurable members are specified

There are two changes this patch makes to the way configurable members of a
state machine are specified in SLICC.  The first change is that the data
member declarations will need to be separated by a semi-colon instead of a
comma.  Secondly, the default value to be assigned would now use SLICC's
assignment operator i.e. ':='.

21 files changed, 106 insertions, 108 deletions

diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
index 5e49d5b13..f707ba963 100644
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -27,12 +27,12 @@
  */
 
 machine(L0Cache, "MESI Directory L0 Cache")
- : Sequencer * sequencer,
-   CacheMemory * Icache,
-   CacheMemory * Dcache,
-   Cycles request_latency = 2,
-   Cycles response_latency = 2,
-   bool send_evictions,
+ : Sequencer * sequencer;
+   CacheMemory * Icache;
+   CacheMemory * Dcache;
+   Cycles request_latency := 2;
+   Cycles response_latency := 2;
+   bool send_evictions;
 {
   // NODE L0 CACHE
   // From this node's L0 cache to the network
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
index 43daa0463..170599a51 100644
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -27,11 +27,11 @@
  */
 
 machine(L1Cache, "MESI Directory L1 Cache CMP")
- : CacheMemory * cache,
-   int l2_select_num_bits,
-   Cycles l1_request_latency = 2,
-   Cycles l1_response_latency = 2,
-   Cycles to_l2_latency = 1,
+ : CacheMemory * cache;
+   int l2_select_num_bits;
+   Cycles l1_request_latency := 2;
+   Cycles l1_response_latency := 2;
+   Cycles to_l2_latency := 1;
 {
   // From this node's L1 cache TO the network
   // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
@@ -40,7 +40,6 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   MessageBuffer responseToL2, network="To", virtual_network="1", ordered="false", vnet_type="response";
   MessageBuffer unblockToL2, network="To", virtual_network="2", ordered="false", vnet_type="unblock";
 
-
   // To this node's L1 cache FROM the network
   // a L2 bank -> this L1
   MessageBuffer requestFromL2, network="From", virtual_network="0", ordered="false", vnet_type="request";
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index a202a8deb..96c1699b7 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -27,16 +27,16 @@
  */
 
 machine(L1Cache, "MESI Directory L1 Cache CMP")
- : Sequencer * sequencer,
-   CacheMemory * L1Icache,
-   CacheMemory * L1Dcache,
-   Prefetcher * prefetcher = 'NULL',
-   int l2_select_num_bits,
-   Cycles l1_request_latency = 2,
-   Cycles l1_response_latency = 2,
-   Cycles to_l2_latency = 1,
-   bool send_evictions,
-   bool enable_prefetch = "False"
+ : Sequencer * sequencer;
+   CacheMemory * L1Icache;
+   CacheMemory * L1Dcache;
+   Prefetcher * prefetcher;
+   int l2_select_num_bits;
+   Cycles l1_request_latency := 2;
+   Cycles l1_response_latency := 2;
+   Cycles to_l2_latency := 1;
+   bool send_evictions;
+   bool enable_prefetch := "False";
 {
   // NODE L1 CACHE
   // From this node's L1 cache TO the network
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
index f69eaa9a9..f191ddccb 100644
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -32,10 +32,10 @@
  */
 
 machine(L2Cache, "MESI Directory L2 Cache CMP")
- : CacheMemory * L2cache,
-   Cycles l2_request_latency = 2,
-   Cycles l2_response_latency = 2,
-   Cycles to_l1_latency = 1
+ : CacheMemory * L2cache;
+   Cycles l2_request_latency := 2;
+   Cycles l2_response_latency := 2;
+   Cycles to_l1_latency := 1;
 {
   // L2 BANK QUEUES
   // From local bank of L2 cache TO the network
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm
index bfd4fc475..679f2dee7 100644
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm
@@ -35,10 +35,10 @@
 
 
 machine(Directory, "MESI Two Level directory protocol")
- : DirectoryMemory * directory,
-   MemoryControl * memBuffer,
-   Cycles to_mem_ctrl_latency = 1,
-   Cycles directory_latency = 6,
+ : DirectoryMemory * directory;
+   MemoryControl * memBuffer;
+   Cycles to_mem_ctrl_latency := 1;
+   Cycles directory_latency := 6;
 {
   MessageBuffer requestToDir, network="From", virtual_network="0",
         ordered="false", vnet_type="request";
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
index b9bb68cbd..80c70c80a 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -28,8 +28,8 @@
  */
 
 machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
-  Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+  Cycles request_latency := 6;
 {
 
   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 561de2397..9b0c18bc8 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -28,11 +28,11 @@
  */
 
 machine(L1Cache, "MI Example L1 Cache")
-: Sequencer * sequencer,
-  CacheMemory * cacheMemory,
-  Cycles cache_response_latency = 12,
-  Cycles issue_latency = 2,
-  bool send_evictions
+: Sequencer * sequencer;
+  CacheMemory * cacheMemory;
+  Cycles cache_response_latency := 12;
+  Cycles issue_latency := 2;
+  bool send_evictions;
 {
 
   // NETWORK BUFFERS
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index 87ed57919..f0d85cba8 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -28,9 +28,9 @@
  */
 
 machine(Directory, "Directory protocol") 
-: DirectoryMemory * directory,
-  MemoryControl * memBuffer,
-  Cycles directory_latency = 12
+: DirectoryMemory * directory;
+  MemoryControl * memBuffer;
+  Cycles directory_latency := 12;
 {
 
   MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward";
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index c9da54f85..14b8c4e4a 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -28,8 +28,8 @@
  */
 
 machine(DMA, "DMA Controller") 
-: DMASequencer * dma_sequencer,
-  Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+  Cycles request_latency := 6;
 {
 
   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index bf935ab65..fb74a67e4 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -27,13 +27,13 @@
  */
 
 machine(L1Cache, "Directory protocol")
- : Sequencer * sequencer,
-   CacheMemory * L1Icache,
-   CacheMemory * L1Dcache,
-   int l2_select_num_bits,
-   Cycles request_latency = 2,
-   Cycles use_timeout_latency = 50,
-   bool send_evictions
+ : Sequencer * sequencer;
+   CacheMemory * L1Icache;
+   CacheMemory * L1Dcache;
+   int l2_select_num_bits;
+   Cycles request_latency := 2;
+   Cycles use_timeout_latency := 50;
+   bool send_evictions;
 {
 
   // NODE L1 CACHE
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index 5974321b7..7d81f4164 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -27,9 +27,9 @@
  */
 
 machine(L2Cache, "Token protocol")
-: CacheMemory * L2cache,
-  Cycles response_latency = 2,
-  Cycles request_latency = 2
+: CacheMemory * L2cache;
+  Cycles response_latency := 2;
+  Cycles request_latency := 2;
 {
 
   // L2 BANK QUEUES
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index 336bb80ee..b403bc91c 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -27,9 +27,9 @@
  */
 
 machine(Directory, "Directory protocol")
-:  DirectoryMemory * directory,
-   MemoryControl * memBuffer,
-   Cycles directory_latency = 6
+:  DirectoryMemory * directory;
+   MemoryControl * memBuffer;
+   Cycles directory_latency := 6;
 {
 
   // ** IN QUEUES **
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index fd1ab6f6c..1a8b3aea9 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -28,9 +28,9 @@
  */
 
 machine(DMA, "DMA Controller") 
-: DMASequencer * dma_sequencer,
-  Cycles request_latency = 14,
-  Cycles response_latency = 14
+: DMASequencer * dma_sequencer;
+  Cycles request_latency := 14;
+  Cycles response_latency := 14;
 {
   MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false", vnet_type="response";
 
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index 238689efa..b1197780f 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -32,22 +32,22 @@
  */
 
 machine(L1Cache, "Token protocol")
- : Sequencer * sequencer,
-   CacheMemory * L1Icache,
-   CacheMemory * L1Dcache,
-   int l2_select_num_bits,
-   int N_tokens,
-
-   Cycles l1_request_latency = 2,
-   Cycles l1_response_latency = 2,
-   int retry_threshold = 1,
-   Cycles fixed_timeout_latency = 100,
-   Cycles reissue_wakeup_latency = 10,
-   Cycles use_timeout_latency = 50,
-
-   bool dynamic_timeout_enabled = true,
-   bool no_mig_atomic = true,
-   bool send_evictions
+ : Sequencer * sequencer;
+   CacheMemory * L1Icache;
+   CacheMemory * L1Dcache;
+   int l2_select_num_bits;
+   int N_tokens;
+
+   Cycles l1_request_latency := 2;
+   Cycles l1_response_latency := 2;
+   int retry_threshold := 1;
+   Cycles fixed_timeout_latency := 100;
+   Cycles reissue_wakeup_latency := 10;
+   Cycles use_timeout_latency := 50;
+
+   bool dynamic_timeout_enabled := "True";
+   bool no_mig_atomic := "True";
+   bool send_evictions;
 {
 
   // From this node's L1 cache TO the network
@@ -206,7 +206,6 @@ machine(L1Cache, "Token protocol")
   Cycles averageLatencyEstimate() {
     DPRINTF(RubySlicc, "%d\n",
             (averageLatencyCounter >> averageLatencyHysteresis));
-    //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
     return averageLatencyCounter >> averageLatencyHysteresis;
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
index f0fa8227d..f8bd01695 100644
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -27,11 +27,11 @@
  */
 
 machine(L2Cache, "Token protocol")
- : CacheMemory * L2cache,
-   int N_tokens,
-   Cycles l2_request_latency = 5,
-   Cycles l2_response_latency = 5,
-   bool filtering_enabled = true
+ : CacheMemory * L2cache;
+   int N_tokens;
+   Cycles l2_request_latency := 5;
+   Cycles l2_response_latency := 5;
+   bool filtering_enabled := "True";
 {
 
   // L2 BANK QUEUES
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index 4354d7c4c..5cb29fcc2 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -27,13 +27,13 @@
  */
 
 machine(Directory, "Token protocol")
- : DirectoryMemory * directory,
-   MemoryControl * memBuffer,
-   int l2_select_num_bits,
-   Cycles directory_latency = 5,
-   bool distributed_persistent = true,
-   Cycles fixed_timeout_latency = 100,
-   Cycles reissue_wakeup_latency = 10
+ : DirectoryMemory * directory;
+   MemoryControl * memBuffer;
+   int l2_select_num_bits;
+   Cycles directory_latency := 5;
+   bool distributed_persistent := "True";
+   Cycles fixed_timeout_latency := 100;
+   Cycles reissue_wakeup_latency := 10;
 {
 
   MessageBuffer dmaResponseFromDir, network="To", virtual_network="5", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index 812017acd..441a001fc 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -28,8 +28,8 @@
 
 
 machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
-  Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+  Cycles request_latency := 6;
 {
 
   MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 514488115..7c150bda0 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -34,15 +34,15 @@
  */
 
 machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
-: Sequencer * sequencer,
-  CacheMemory * L1Icache,
-  CacheMemory * L1Dcache,
-  CacheMemory * L2cache,
-  Cycles cache_response_latency = 10,
-  Cycles issue_latency = 2,
-  Cycles l2_cache_hit_latency = 10,
-  bool no_mig_atomic = true,
-  bool send_evictions
+: Sequencer * sequencer;
+  CacheMemory * L1Icache;
+  CacheMemory * L1Dcache;
+  CacheMemory * L2cache;
+  Cycles cache_response_latency := 10;
+  Cycles issue_latency := 2;
+  Cycles l2_cache_hit_latency := 10;
+  bool no_mig_atomic := "True";
+  bool send_evictions;
 {
 
   // NETWORK BUFFERS
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 58e4d7346..4e2f846e2 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -34,12 +34,12 @@
  */
 
 machine(Directory, "AMD Hammer-like protocol") 
-: DirectoryMemory * directory,
-  CacheMemory * probeFilter,
-  MemoryControl * memBuffer,
-  Cycles memory_controller_latency = 2,
-  bool probe_filter_enabled = false,
-  bool full_bit_dir_enabled = false
+: DirectoryMemory * directory;
+  CacheMemory * probeFilter;
+  MemoryControl * memBuffer;
+  Cycles memory_controller_latency := 2;
+  bool probe_filter_enabled := "False";
+  bool full_bit_dir_enabled := "False";
 {
 
   MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward";
diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm
index 1d0f67881..e4d26bb48 100644
--- a/src/mem/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/protocol/MOESI_hammer-dma.sm
@@ -28,8 +28,8 @@
 
 
 machine(DMA, "DMA Controller") 
-: DMASequencer * dma_sequencer,
-  Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+  Cycles request_latency := 6;
 {
 
   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm
index 885bbacbe..f69aecd93 100644
--- a/src/mem/protocol/Network_test-cache.sm
+++ b/src/mem/protocol/Network_test-cache.sm
@@ -32,8 +32,8 @@
 
 
 machine(L1Cache, "Network_test L1 Cache")
-: Sequencer * sequencer,
-  Cycles issue_latency = 2
+: Sequencer * sequencer;
+  Cycles issue_latency := 2;
 {
 
   // NETWORK BUFFERS