diff options
| author | Derek Hower <drh5@cs.wisc.edu> | 2009-09-10 22:02:13 -0500 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2009-09-10 22:02:13 -0500 |
| commit | 1e40ee4ea081908782dd7ba159b9f680d933855c (patch) | |
| tree | 86ea0a84a133b237eb1cd4c0f790765ae08905fb /src/mem/protocol | |
| parent | ca0e0c368357f1e31b69c92ada4e3021b84d5560 (diff) | |
| parent | 0637fe0bfd626711b2535cbdf5c40ba67fa7cdfe (diff) | |
| download | gem5-1e40ee4ea081908782dd7ba159b9f680d933855c.tar.xz | |
Automated merge with ssh://hg@m5sim.org/m5
Diffstat (limited to 'src/mem/protocol')
| -rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 915a0eb99..64771bac5 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -17,6 +17,7 @@ machine(L1Cache, "MI Example L1 Cache") II, desc="Not Present/Invalid, issued PUT"; M, desc="Modified"; MI, desc="Modified, issued PUT"; + MII, desc="Modified, issued PUTX, received nack"; IS, desc="Issued request for LOAD/IFETCH"; IM, desc="Issued request for STORE/ATOMIC"; @@ -388,6 +389,16 @@ machine(L1Cache, "MI Example L1 Cache") o_popForwardedRequestQueue; } + transition(MI, Writeback_Nack, MII) { + o_popForwardedRequestQueue; + } + + transition(MII, Fwd_GETX, I) { + ee_sendDataFromTBE; + w_deallocateTBE; + o_popForwardedRequestQueue; + } + transition(II, Writeback_Nack, I) { w_deallocateTBE; o_popForwardedRequestQueue; |