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authorNilay Vaish <nilay@cs.wisc.edu>2013-02-10 21:43:10 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-02-10 21:43:10 -0600
commit253e8edf13c4d7bee6bd13f84fdfa6cf40a0c5c3 (patch)
treede95d79e40d3e755ccc9919607175fcf41bf56f5 /src/mem/protocol
parentf6e3ab7bd4d6c27fd400c718bfe225b09a3b486b (diff)
downloadgem5-253e8edf13c4d7bee6bd13f84fdfa6cf40a0c5c3.tar.xz
ruby: replace Time with Cycles (final patch in the series)
This patch is as of now the final patch in the series of patches that replace Time with Cycles.This patch further replaces Time with Cycles in Sequencer, Profiler, different protocols and related entities. Though Time has not been completely removed, the places where it is in use seem benign as of now.
Diffstat (limited to 'src/mem/protocol')
-rw-r--r--src/mem/protocol/MOESI_CMP_token-L1cache.sm6
-rw-r--r--src/mem/protocol/MOESI_hammer-cache.sm12
-rw-r--r--src/mem/protocol/MOESI_hammer-dir.sm2
-rw-r--r--src/mem/protocol/MOESI_hammer-msg.sm14
-rw-r--r--src/mem/protocol/RubySlicc_Exports.sm3
-rw-r--r--src/mem/protocol/RubySlicc_Profiler.sm2
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm10
-rw-r--r--src/mem/protocol/RubySlicc_Util.sm7
8 files changed, 32 insertions, 24 deletions
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index 365a963b9..02737a4f6 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -153,7 +153,7 @@ machine(L1Cache, "Token protocol")
bool IsAtomic, default="false", desc="Request was an atomic request";
AccessType AccessType, desc="Type of request (used for profiling)";
- Time IssueTime, desc="Time the request was issued";
+ Cycles IssueTime, desc="Time the request was issued";
RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
@@ -183,7 +183,7 @@ machine(L1Cache, "Token protocol")
void unset_tbe();
void wakeUpAllBuffers();
void wakeUpBuffers(Address a);
- Time curCycle();
+ Cycles curCycle();
TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
@@ -1452,7 +1452,7 @@ machine(L1Cache, "Token protocol")
// Update average latency
if (tbe.IssueCount <= 1) {
if (tbe.ExternalResponse == true) {
- updateAverageLatencyEstimate(TimeToCycles(curCycle() - tbe.IssueTime));
+ updateAverageLatencyEstimate(curCycle() - tbe.IssueTime);
}
}
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index fc2a9da90..bc3b700d3 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -161,9 +161,13 @@ machine(L1Cache, "AMD Hammer-like protocol")
bool AppliedSilentAcks, default="false", desc="for full-bit dir, does the pending msg count reflect the silent acks";
MachineID LastResponder, desc="last machine to send a response for this request";
MachineID CurOwner, desc="current owner of the block, used for UnblockS responses";
- Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache";
- Time ForwardRequestTime, default="0", desc="time the dir forwarded the request";
- Time FirstResponseTime, default="0", desc="the time the first response was received";
+
+ Cycles InitialRequestTime, default="Cycles(0)",
+ desc="time the initial requests was sent from the L1Cache";
+ Cycles ForwardRequestTime, default="Cycles(0)",
+ desc="time the dir forwarded the request";
+ Cycles FirstResponseTime, default="Cycles(0)",
+ desc="the time the first response was received";
}
structure(TBETable, external="yes") {
@@ -181,7 +185,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
void unset_tbe();
void wakeUpAllBuffers();
void wakeUpBuffers(Address a);
- Time curCycle();
+ Cycles curCycle();
Entry getCacheEntry(Address address), return_by_pointer="yes" {
Entry L2cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address));
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 40f4db73e..e1ed2feef 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -179,7 +179,7 @@ machine(Directory, "AMD Hammer-like protocol")
void set_tbe(TBE a);
void unset_tbe();
void wakeUpBuffers(Address a);
- Time curCycle();
+ Cycles curCycle();
// ** OBJECTS **
diff --git a/src/mem/protocol/MOESI_hammer-msg.sm b/src/mem/protocol/MOESI_hammer-msg.sm
index 41d176a9c..eef78ba45 100644
--- a/src/mem/protocol/MOESI_hammer-msg.sm
+++ b/src/mem/protocol/MOESI_hammer-msg.sm
@@ -94,8 +94,11 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
NetDest Destination, desc="Multicast destination mask";
MessageSizeType MessageSize, desc="size category of the message";
bool DirectedProbe, default="false", desc="probe filter directed probe";
- Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache";
- Time ForwardRequestTime, default="0", desc="time the dir forwarded the request";
+
+ Cycles InitialRequestTime, default="Cycles(0)",
+ desc="time the initial requests was sent from the L1Cache";
+ Cycles ForwardRequestTime, default="Cycles(0)",
+ desc="time the dir forwarded the request";
int SilentAcks, default="0", desc="silent acks from the full-bit directory";
bool functionalRead(Packet *pkt) {
@@ -120,8 +123,11 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
bool Dirty, desc="Is the data dirty (different than memory)?";
int Acks, default="0", desc="How many messages this counts as";
MessageSizeType MessageSize, desc="size category of the message";
- Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache";
- Time ForwardRequestTime, default="0", desc="time the dir forwarded the request";
+
+ Cycles InitialRequestTime, default="Cycles(0)",
+ desc="time the initial requests was sent from the L1Cache";
+ Cycles ForwardRequestTime, default="Cycles(0)",
+ desc="time the dir forwarded the request";
int SilentAcks, default="0", desc="silent acks from the full-bit directory";
bool functionalRead(Packet *pkt) {
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index 8ca1ed32c..036419095 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -33,11 +33,10 @@ external_type(bool, primitive="yes", default="false");
external_type(std::string, primitive="yes");
external_type(uint32_t, primitive="yes");
external_type(uint64, primitive="yes");
-external_type(Time, primitive="yes", default="0");
external_type(PacketPtr, primitive="yes");
external_type(Packet, primitive="yes");
external_type(Address);
-external_type(Cycles, primitive="yes");
+external_type(Cycles, primitive="yes", default="Cycles(0)");
structure(DataBlock, external = "yes", desc="..."){
void clear();
diff --git a/src/mem/protocol/RubySlicc_Profiler.sm b/src/mem/protocol/RubySlicc_Profiler.sm
index 64f643054..e09f30056 100644
--- a/src/mem/protocol/RubySlicc_Profiler.sm
+++ b/src/mem/protocol/RubySlicc_Profiler.sm
@@ -47,4 +47,4 @@ void profile_outstanding_persistent_request(int outstanding);
void profile_average_latency_estimate(int latency);
// profile the total message delay of a message across a virtual network
-void profileMsgDelay(int virtualNetwork, Time delayCycles);
+void profileMsgDelay(int virtualNetwork, Cycles delayCycles);
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 0f6cd0b96..096215386 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -41,7 +41,7 @@ external_type(OutPort, primitive="yes");
structure(InPort, external = "yes", primitive="yes") {
bool isReady();
void dequeue();
- Time dequeue_getDelayCycles();
+ Cycles dequeue_getDelayCycles();
void recycle();
bool isEmpty();
}
@@ -97,10 +97,14 @@ structure (NetDest, external = "yes", non_obj="yes") {
structure (Sequencer, external = "yes") {
void readCallback(Address, DataBlock);
void readCallback(Address, GenericMachineType, DataBlock);
- void readCallback(Address, GenericMachineType, DataBlock, Time, Time, Time);
+ void readCallback(Address, GenericMachineType, DataBlock,
+ Cycles, Cycles, Cycles);
+
void writeCallback(Address, DataBlock);
void writeCallback(Address, GenericMachineType, DataBlock);
- void writeCallback(Address, GenericMachineType, DataBlock, Time, Time, Time);
+ void writeCallback(Address, GenericMachineType, DataBlock,
+ Cycles, Cycles, Cycles);
+
void checkCoherence(Address);
void profileNack(Address, int, int, uint64);
void evictionCallback(Address);
diff --git a/src/mem/protocol/RubySlicc_Util.sm b/src/mem/protocol/RubySlicc_Util.sm
index 238884503..0d0e63d85 100644
--- a/src/mem/protocol/RubySlicc_Util.sm
+++ b/src/mem/protocol/RubySlicc_Util.sm
@@ -32,14 +32,9 @@
void error(std::string msg);
void assert(bool condition);
int random(int number);
-Time zero_time();
-Cycles TimeToCycles(Time t);
+Cycles zero_time();
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
-int time_to_int(Time time);
-Time getTimeModInt(Time time, int modulus);
-Time getTimePlusInt(Time addend1, int addend2);
-Time getTimeMinusTime(Time t1, Time t2);
void procProfileCoherenceRequest(NodeID node, bool needCLB);
void dirProfileCoherenceRequest(NodeID node, bool needCLB);
int max_tokens();