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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-07-06 18:45:15 -0700
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-07-06 18:45:15 -0700
commit255f82a78320fed364cfa45bf0e65b341ab0bcb7 (patch)
treed84e2290c795701003f164f650cdd738ab00dc14 /src/mem/protocol
parent4f833907812b50e8c6cce761d2f3c1f6fd07ae7b (diff)
downloadgem5-255f82a78320fed364cfa45bf0e65b341ab0bcb7.tar.xz
ruby: added generic dma machine
Diffstat (limited to 'src/mem/protocol')
-rw-r--r--src/mem/protocol/RubySlicc_Exports.sm1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index 2e4a16784..e8616521a 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -173,6 +173,7 @@ enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
L2Cache, desc="L2 Cache Mach";
L3Cache, desc="L3 Cache Mach";
Directory, desc="Directory Mach";
+ DMA, desc="DMA Mach";
Collector, desc="Collector Mach";
L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";