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authorBlake Hechtman <blake.hechtman@amd.com>2015-07-20 09:15:18 -0500
committerBlake Hechtman <blake.hechtman@amd.com>2015-07-20 09:15:18 -0500
commit34fb6b5e35db751f310aee824046107e57a0ba03 (patch)
tree4f07b86c4d50f0431a8451406026a693ccbb1e39 /src/mem/protocol
parentb7ea2bc705bfae2e7719d6259cc14de95f4f991d (diff)
downloadgem5-34fb6b5e35db751f310aee824046107e57a0ba03.tar.xz
mem: misc flags for AMD gpu model
This patch add support to mark memory requests/packets with attributes defined in HSA, such as memory order and scope.
Diffstat (limited to 'src/mem/protocol')
-rw-r--r--src/mem/protocol/RubySlicc_Exports.sm25
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm2
2 files changed, 25 insertions, 2 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index 617989d15..6fedfeb2d 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -41,7 +41,7 @@ external_type(Tick, primitive="yes", default="0");
structure(DataBlock, external = "yes", desc="..."){
void clear();
- void copyPartial(DataBlock, int, int);
+ void atomicPartial(DataBlock, WriteMask);
}
bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt);
@@ -78,6 +78,26 @@ enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent")
NotPresent, desc="block is NotPresent";
Busy, desc="block is in a transient state, currently invalid";
}
+//HSA scopes
+enumeration(HSAScope, desc="...", default="HSAScope_UNSPECIFIED") {
+ UNSPECIFIED, desc="Unspecified scope";
+ NOSCOPE, desc="Explictly unscoped";
+ WAVEFRONT, desc="Wavefront scope";
+ WORKGROUP, desc="Workgroup scope";
+ DEVICE, desc="Device scope";
+ SYSTEM, desc="System scope";
+}
+
+// HSA segment types
+enumeration(HSASegment, desc="...", default="HSASegment_GLOBAL") {
+ GLOBAL, desc="Global segment";
+ GROUP, desc="Group segment";
+ PRIVATE, desc="Private segment";
+ KERNARG, desc="Kernarg segment";
+ READONLY, desc="Readonly segment";
+ SPILL, desc="Spill segment";
+ ARG, desc="Arg segment";
+}
// TesterStatus
enumeration(TesterStatus, desc="...") {
@@ -143,9 +163,10 @@ enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
}
enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
- Default, desc="Replace this with access_types passed to the DMA Ruby object";
+ Default, desc="Replace this with access_types passed to the DMA Ruby object";
LD, desc="Load";
ST, desc="Store";
+ FLUSH, desc="Flush request type";
NULL, desc="Invalid request type";
}
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 8e846098c..c7479089b 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -126,6 +126,8 @@ structure(RubyRequest, desc="...", interface="Message", external="yes") {
int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
int contextId, desc="this goes away but must be replace with Nilay";
+ HSAScope scope, desc="HSA scope";
+ HSASegment segment, desc="HSA segment";
}
structure(AbstractEntry, primitive="yes", external = "yes") {