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| author | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
|---|---|---|
| committer | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
| commit | 74ca89f8b7d9b340d1d4f83511b57a2dfa2a70df (patch) | |
| tree | d5763275304cbe0d6c662130a14b9459b29d5936 /src/mem/protocol | |
| parent | 536e3664e41d406af1e618dd02c3222f7cbbcaee (diff) | |
| download | gem5-74ca89f8b7d9b340d1d4f83511b57a2dfa2a70df.tar.xz | |
ruby: give access to cache tag/data latencies from SLICC
This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.
Diffstat (limited to 'src/mem/protocol')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Types.sm | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index fb506781c..88b9839bb 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -149,6 +149,8 @@ structure (CacheMemory, external = "yes") { void deallocate(Address); AbstractCacheEntry lookup(Address); bool isTagPresent(Address); + Cycles getTagLatency(); + Cycles getDataLatency(); void setMRU(Address); void recordRequestType(CacheRequestType); bool checkResourceAvailable(CacheResourceType, Address); |