ruby: banked cache array resource model

This patch models a cache as separate tag and data arrays.  The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute.  This is similar to how TBE entries and slots
in output ports are modeled.

2 files changed, 7 insertions, 0 deletions

diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index ef752c604..92739385b 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -184,6 +184,11 @@ enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
   TagArrayWrite,    desc="Write access to the cache's tag array";
 }
 
+enumeration(CacheResourceType, desc="...", default="CacheResourceType_NULL") {
+  DataArray,    desc="Access to the cache's data array";
+  TagArray,     desc="Access to the cache's tag array";
+}
+
 enumeration(DirectoryRequestType, desc="...", default="DirectoryRequestType_NULL") {
   Default,    desc="Replace this with access_types passed to the Directory Ruby object";
 }
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 436b39273..a14af946c 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -109,6 +109,7 @@ structure (Sequencer, external = "yes") {
   void profileNack(Address, int, int, uint64);
   void evictionCallback(Address);
   void recordRequestType(SequencerRequestType);
+  bool checkResourceAvailable(CacheResourceType, Address);
 }
 
 structure(RubyRequest, desc="...", interface="Message", external="yes") {
@@ -154,6 +155,7 @@ structure (CacheMemory, external = "yes") {
 
   void setMRU(Address);
   void recordRequestType(CacheRequestType);
+  bool checkResourceAvailable(CacheResourceType, Address);
 }
 
 structure (WireBuffer, inport="yes", outport="yes", external = "yes") {