diff options
| author | Dibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <gope@wisc.edu> | 2013-02-28 10:04:26 -0600 |
|---|---|---|
| committer | Dibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <gope@wisc.edu> | 2013-02-28 10:04:26 -0600 |
| commit | c636a09e83b08c27ce60a0f1d13536d736a06926 (patch) | |
| tree | 06f6c03aa546d90b18752f218b52d84c6f1eb96e /src/mem/protocol | |
| parent | 82cf1565d02608111459379634c6daa31d4a6895 (diff) | |
| download | gem5-c636a09e83b08c27ce60a0f1d13536d736a06926.tar.xz | |
ruby: mesi coherence protocol: invalidate lock
The MESI CMP directory coherence protocol, while transitioning from SM to IM,
did not invalidate the lock that it might have taken on a cache line. This
patch adds an action for doing so.
The problem was found by Dibakar, but I was not happy with his proposed
solution. So I implemented a different solution.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/protocol')
| -rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L1cache.sm | 13 | ||||
| -rw-r--r-- | src/mem/protocol/RubySlicc_Types.sm | 1 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index 113421842..f8d731ee1 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -782,6 +782,11 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } } + action(dg_invalidate_sc, "dg", + desc="Invalidate store conditional as the cache lost permissions") { + sequencer.invalidateSC(address); + } + action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); @@ -1251,7 +1256,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } // Transitions from IM - transition({IM, SM}, Inv, IM) { + transition(IM, Inv, IM) { fi_sendInvAck; l_popRequestQueue; } @@ -1292,6 +1297,12 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } // transitions from SM + transition(SM, Inv, IM) { + fi_sendInvAck; + dg_invalidate_sc; + l_popRequestQueue; + } + transition({SM, IM, PF_SM, PF_IM}, Ack) { q_updateAckCount; o_popIncomingResponseQueue; diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index 096215386..c94020792 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -110,6 +110,7 @@ structure (Sequencer, external = "yes") { void evictionCallback(Address); void recordRequestType(SequencerRequestType); bool checkResourceAvailable(CacheResourceType, Address); + void invalidateSC(Address); } structure(RubyRequest, desc="...", interface="Message", external="yes") { |