ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.

14 files changed, 149 insertions, 160 deletions

diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index 57a147900..fb78623cd 100644
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -329,8 +329,8 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                                                   l2_select_low_bit, l2_select_num_bits));
-        DEBUG_EXPR(address);
-        //DEBUG_EXPR(out_msg.Destination);
+        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+                address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -346,8 +346,8 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                                                   l2_select_low_bit, l2_select_num_bits));
-        DEBUG_EXPR(address);
-        //DEBUG_EXPR(out_msg.Destination);
+        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+                address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -362,11 +362,11 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
         out_msg.Address := address;
         out_msg.Type := CoherenceRequestType:GETX;
         out_msg.Requestor := machineID;
-        //DEBUG_EXPR(machineID);
+        DPRINTF(RubySlicc, "%s\n", machineID);
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                                                   l2_select_low_bit, l2_select_num_bits));
-        DEBUG_EXPR(address);
-        //DEBUG_EXPR(out_msg.Destination);
+        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+                address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -382,8 +382,8 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                                                   l2_select_low_bit, l2_select_num_bits));
-        DEBUG_EXPR(address);
-        //DEBUG_EXPR(out_msg.Destination);
+        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+                address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -522,7 +522,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                                                   l2_select_low_bit, l2_select_num_bits));
       out_msg.MessageSize := MessageSizeType:Response_Control;
-      DEBUG_EXPR(address);
+      DPRINTF(RubySlicc, "%s\n", address);
       
     }
   }
@@ -535,7 +535,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                                                   l2_select_low_bit, l2_select_num_bits));
       out_msg.MessageSize := MessageSizeType:Response_Control;
-      DEBUG_EXPR(address);
+      DPRINTF(RubySlicc, "%s\n", address);
 
     }
   }
@@ -543,12 +543,12 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
 
 
   action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
-    //DEBUG_EXPR(getL1CacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getL1CacheEntry(address).DataBlk);
     sequencer.readCallback(address, getL1CacheEntry(address).DataBlk);
   }
 
   action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
-    //DEBUG_EXPR(getL1CacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getL1CacheEntry(address).DataBlk);
     sequencer.writeCallback(address, getL1CacheEntry(address).DataBlk);
     getL1CacheEntry(address).Dirty := true;
   }
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index 8a8f62314..98502df0f 100644
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -188,9 +188,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   }
 
   void addSharer(Address addr, MachineID requestor) {
-    //DEBUG_EXPR(machineID);
-    //DEBUG_EXPR(requestor);
-    //DEBUG_EXPR(addr);
+    DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
+            machineID, requestor, addr);
     getL2CacheEntry(addr).Sharers.add(requestor);
   }
 
@@ -251,8 +250,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
         return Event:L1_PUTX_old;
       }
     } else {
-      DEBUG_EXPR(addr);
-      DEBUG_EXPR(type);
+      DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
       error("Invalid L1 forwarded request type");
     }
   }
@@ -267,11 +265,9 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache) {
     if(L1unblockNetwork_in.isReady()) {
       peek(L1unblockNetwork_in,  ResponseMsg) {
-        DEBUG_EXPR(in_msg.Address);
-	DEBUG_EXPR(getState(in_msg.Address));
-        DEBUG_EXPR(in_msg.Sender);
-        DEBUG_EXPR(in_msg.Type);
-        DEBUG_EXPR(in_msg.Destination);
+        DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
+                in_msg.Address, getState(in_msg.Address), in_msg.Sender,
+                in_msg.Type, in_msg.Destination);
 
         assert(in_msg.Destination.isElement(machineID));
         if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
@@ -329,12 +325,9 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache) {
     if(L1RequestIntraChipL2Network_in.isReady()) {
       peek(L1RequestIntraChipL2Network_in,  RequestMsg) {
-        DEBUG_EXPR(in_msg.Address);
-        //DEBUG_EXPR(id);
-        DEBUG_EXPR(getState(in_msg.Address));
-        //DEBUG_EXPR(in_msg.Requestor);
-        DEBUG_EXPR(in_msg.Type);
-        //DEBUG_EXPR(in_msg.Destination);
+        DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
+                in_msg.Address, getState(in_msg.Address), in_msg.Requestor,
+                in_msg.Type, in_msg.Destination);
         assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
         assert(in_msg.Destination.isElement(machineID));
         if (L2cacheMemory.isTagPresent(in_msg.Address)) {
@@ -506,12 +499,11 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.Sender := machineID;
       out_msg.Destination.add(L2_TBEs[address].L1_GetX_ID);
-      //DEBUG_EXPR(out_msg.Destination);
+      DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
       out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
       out_msg.Dirty := getL2CacheEntry(address).Dirty;
-      DEBUG_EXPR(out_msg.Address);
-      //DEBUG_EXPR(out_msg.Destination);
-      //DEBUG_EXPR(out_msg.DataBlk);
+      DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
+              out_msg.Address, out_msg.Destination, out_msg.DataBlk);
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
   }
diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm
index ceba6c425..8fa8eedc5 100644
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm
@@ -167,7 +167,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
           trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address));          
         } else {
-          DEBUG_EXPR(in_msg);
+          DPRINTF(RubySlicc, "%s\n", in_msg);
           error("Invalid message");
         }
       }
@@ -183,7 +183,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         } else if (in_msg.Type == CoherenceResponseType:ACK) {
           trigger(Event:CleanReplacement, in_msg.Address);
         } else {
-          DEBUG_EXPR(in_msg.Type);
+          DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
         }
       }
@@ -199,7 +199,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
           trigger(Event:Memory_Ack, in_msg.Address);
         } else {
-          DEBUG_EXPR(in_msg.Type);
+          DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
         }
       }
@@ -271,7 +271,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         out_msg.Prefetch := in_msg.Prefetch;
         out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
 
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -287,7 +287,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         out_msg.MessageSize := in_msg.MessageSize;
         //out_msg.Prefetch := in_msg.Prefetch;
 
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -295,8 +295,8 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
     peek(responseNetwork_in, ResponseMsg) {
       getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
-      DEBUG_EXPR(in_msg.Address);
-      DEBUG_EXPR(in_msg.DataBlk);
+      DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+              in_msg.Address, in_msg.DataBlk);
     }
   }
 //added by SS for dma
@@ -309,7 +309,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         out_msg.OriginalRequestorMachId := machineID;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -349,7 +349,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         out_msg.MessageSize := in_msg.MessageSize;
         //out_msg.Prefetch := in_msg.Prefetch;
 
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -439,7 +439,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         out_msg.MessageSize := in_msg.MessageSize;
         //out_msg.Prefetch := in_msg.Prefetch;
    
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 84975ffd5..8232e93e1 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -273,7 +273,7 @@ machine(L1Cache, "MI Example L1 Cache")
   }
 
   action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
     sequencer.readCallback(address, 
                            GenericMachineType:L1Cache,
                            getCacheEntry(address).DataBlk);
@@ -281,7 +281,7 @@ machine(L1Cache, "MI Example L1 Cache")
 
   action(rx_load_hit, "rx", desc="External load completed.") {
     peek(responseNetwork_in, ResponseMsg) {
-      DEBUG_EXPR(getCacheEntry(address).DataBlk);
+      DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
       sequencer.readCallback(address, 
                              getNondirectHitMachType(in_msg.Sender),
                              getCacheEntry(address).DataBlk);
@@ -289,7 +289,7 @@ machine(L1Cache, "MI Example L1 Cache")
   }
 
   action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
     sequencer.writeCallback(address, 
                             GenericMachineType:L1Cache,
                             getCacheEntry(address).DataBlk);
@@ -297,7 +297,7 @@ machine(L1Cache, "MI Example L1 Cache")
 
   action(sx_store_hit, "sx", desc="External store completed.") {
     peek(responseNetwork_in, ResponseMsg) {
-      DEBUG_EXPR(getCacheEntry(address).DataBlk);
+      DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
       sequencer.writeCallback(address, 
                               getNondirectHitMachType(in_msg.Sender),
                               getCacheEntry(address).DataBlk);
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index cb274553e..dfb95aedd 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -167,7 +167,7 @@ machine(Directory, "Directory protocol")
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
           trigger(Event:Memory_Ack, in_msg.Address);
         } else {
-          DEBUG_EXPR(in_msg.Type);
+          DPRINTF(RubySlicc,"%s\n", in_msg.Type);
           error("Invalid message");
         }
       }
@@ -369,7 +369,7 @@ machine(Directory, "Directory protocol")
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc,"%s\n", out_msg);
       }
     }
   }
@@ -383,7 +383,7 @@ machine(Directory, "Directory protocol")
         //out_msg.OriginalRequestorMachId := machineID;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc,"%s\n", out_msg);
       }
     }
   }
@@ -399,7 +399,7 @@ machine(Directory, "Directory protocol")
         out_msg.MessageSize := in_msg.MessageSize;
         //out_msg.Prefetch := in_msg.Prefetch;
 
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc,"%s\n", out_msg);
       }
     }
   }
@@ -416,7 +416,7 @@ machine(Directory, "Directory protocol")
         out_msg.MessageSize := in_msg.MessageSize;
         //out_msg.Prefetch := in_msg.Prefetch;
 
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc,"%s\n", out_msg);
       }
     }
   }
@@ -434,7 +434,7 @@ machine(Directory, "Directory protocol")
         out_msg.MessageSize := in_msg.MessageSize;
         //out_msg.Prefetch := in_msg.Prefetch;
 
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc,"%s\n", out_msg);
       }
     }
   }
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index 3f9980d67..31de269a9 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -298,8 +298,7 @@ machine(L1Cache, "Directory protocol")
     if (requestNetwork_in.isReady()) {
       peek(requestNetwork_in, RequestMsg, block_on="Address") {
         assert(in_msg.Destination.isElement(machineID));
-        DEBUG_EXPR("MRM_DEBUG: L1 received");
-        DEBUG_EXPR(in_msg.Type);
+        DPRINTF(RubySlicc, "L1 received: %s\n", in_msg.Type);
 if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) {
           if (in_msg.Requestor == machineID && in_msg.RequestorMachine == MachineType:L1Cache) {
             trigger(Event:Own_GETX, in_msg.Address);
@@ -479,8 +478,7 @@ if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestT
           out_msg.Acks := in_msg.Acks;
           out_msg.MessageSize := MessageSizeType:Response_Data;
         }
-        DEBUG_EXPR("Sending data to L2");
-        DEBUG_EXPR(in_msg.Address);
+        DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.Address);
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
@@ -494,7 +492,7 @@ if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestT
           out_msg.Acks := in_msg.Acks;
           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
         }
-        DEBUG_EXPR("Sending data to L1");
+        DPRINTF(RubySlicc, "Sending data to L1\n");
       }
     }
   }
@@ -529,7 +527,7 @@ if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestT
           out_msg.Acks := in_msg.Acks;
           out_msg.MessageSize := MessageSizeType:Response_Data;
         }
-        DEBUG_EXPR("Sending exclusive data to L2");
+        DPRINTF(RubySlicc, "Sending exclusive data to L2\n");
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
@@ -543,7 +541,7 @@ if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestT
           out_msg.Acks := in_msg.Acks;
           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
         }
-        DEBUG_EXPR("Sending exclusive data to L1");
+        DPRINTF(RubySlicc, "Sending exclusive data to L1\n");
       }
     }
   }
@@ -599,12 +597,12 @@ if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestT
   }
 
   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
     sequencer.readCallback(address, getCacheEntry(address).DataBlk);
   }
 
   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
     sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
     getCacheEntry(address).Dirty := true;
   }
@@ -634,8 +632,7 @@ if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestT
 
   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
     peek(responseToL1Cache_in, ResponseMsg) {
-      DEBUG_EXPR("MRM_DEBUG: L1 decrementNumberOfMessages");
-      DEBUG_EXPR(in_msg.Acks);
+      DPRINTF(RubySlicc, "L1 decrementNumberOfMessages: %d\n", in_msg.Acks);
       TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - in_msg.Acks;
     }
   }
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index 0316e2310..7c6021bae 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -742,8 +742,8 @@ machine(L2Cache, "Token protocol")
       out_msg.Dirty := false;
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(L2_TBEs[address].DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+		        address, L2_TBEs[address].DataBlk);
   }
 
   action(c_sendDataFromTBEToL1GETX, "\c", desc="Send data from TBE to L1 requestors in TBE") {
@@ -758,8 +758,8 @@ machine(L2Cache, "Token protocol")
       out_msg.Acks := L2_TBEs[address].Local_GETX_IntAcks;
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(L2_TBEs[address].DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, L2_TBEs[address].DataBlk);
   }
 
   action(c_sendExclusiveDataFromTBEToL1GETS, "\cc", desc="Send data from TBE to L1 requestors in TBE") {
@@ -802,8 +802,8 @@ machine(L2Cache, "Token protocol")
       out_msg.Acks := L2_TBEs[address].Fwd_GETX_ExtAcks;
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(L2_TBEs[address].DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, L2_TBEs[address].DataBlk);
   }
 
   action(c_sendExclusiveDataFromTBEToFwdGETS, "\ccc", desc="Send data from TBE to external GETX") {
@@ -818,8 +818,8 @@ machine(L2Cache, "Token protocol")
       out_msg.Acks := L2_TBEs[address].Fwd_GETX_ExtAcks;
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(L2_TBEs[address].DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, L2_TBEs[address].DataBlk);
   }
 
   action(d_sendDataToL1GETS, "d", desc="Send data directly to L1 requestor") {
@@ -836,8 +836,8 @@ machine(L2Cache, "Token protocol")
         out_msg.MessageSize := MessageSizeType:ResponseL2hit_Data;
       }
     }
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getL2CacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, getL2CacheEntry(address).DataBlk);
   }
 
   action(d_sendDataToL1GETX, "\d", desc="Send data and a token from TBE to L1 requestor") {
@@ -854,8 +854,8 @@ machine(L2Cache, "Token protocol")
         out_msg.Acks := L2_TBEs[address].Local_GETX_IntAcks;
       }
     }
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getL2CacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, getL2CacheEntry(address).DataBlk);
   }
 
   action(dd_sendDataToFwdGETX, "dd", desc="send data") {
@@ -872,8 +872,8 @@ machine(L2Cache, "Token protocol")
         out_msg.Acks := in_msg.Acks;
       }
     }
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getL2CacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, getL2CacheEntry(address).DataBlk);
   }
 
 
@@ -891,8 +891,8 @@ machine(L2Cache, "Token protocol")
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
     }
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getL2CacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, getL2CacheEntry(address).DataBlk);
   }
 
   action(dd_sendExclusiveDataToFwdGETS, "\d\d", desc="send data") {
@@ -950,12 +950,12 @@ machine(L2Cache, "Token protocol")
 
   action(ee_sendLocalInv, "\ee", desc="Send local invalidates") {
     L2_TBEs[address].NumIntPendingAcks := countLocalSharers(address);
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getLocalSharers(address));
-    DEBUG_EXPR(L2_TBEs[address].NumIntPendingAcks);
+    DPRINTF(RubySlicc, "Address: %s, Local Sharers: %s, Pending Acks: %d\n",
+            address, getLocalSharers(address),
+            L2_TBEs[address].NumIntPendingAcks);
     if (isLocalOwnerValid(address)) {
       L2_TBEs[address].NumIntPendingAcks := L2_TBEs[address].NumIntPendingAcks + 1;
-      DEBUG_EXPR(getLocalOwner(address));
+      DPRINTF(RubySlicc, "%s\n", getLocalOwner(address));
     }
 
     enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index 74a785808..36e96cf41 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -256,7 +256,7 @@ machine(Directory, "Directory protocol")
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
           trigger(Event:Memory_Ack, in_msg.Address);
         } else {
-          DEBUG_EXPR(in_msg.Type);
+          DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
         }
       }
@@ -409,16 +409,16 @@ machine(Directory, "Directory protocol")
       assert(in_msg.Dirty);
       assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
       getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
-      DEBUG_EXPR(in_msg.Address);
-      DEBUG_EXPR(in_msg.DataBlk);
+      DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+              in_msg.Address, in_msg.DataBlk);
     }
   }
 
   action(p_writeFwdDataToMemory, "p", desc="Write Response data to memory") {
      peek(unblockNetwork_in, ResponseMsg) {
       getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
-      DEBUG_EXPR(in_msg.Address);
-      DEBUG_EXPR(in_msg.DataBlk);
+      DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+              in_msg.Address, in_msg.DataBlk);
     }
  }
 
@@ -470,7 +470,7 @@ machine(Directory, "Directory protocol")
         if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
           out_msg.Acks := out_msg.Acks - 1;
         }
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -490,7 +490,7 @@ machine(Directory, "Directory protocol")
         // Not used:
         out_msg.ReadX := false;
         out_msg.Acks := getDirectoryEntry(address).Sharers.count();  // for dma requests
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -508,7 +508,7 @@ machine(Directory, "Directory protocol")
         // Not used:
         out_msg.ReadX := false;
         out_msg.Acks := getDirectoryEntry(address).Sharers.count();  // for dma requests
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
diff --git a/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm b/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
index 7717434f8..52d6ca48b 100644
--- a/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
@@ -333,8 +333,8 @@ machine(Directory, "Directory protocol") {
       assert(in_msg.Dirty);
       assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
       directory[in_msg.Address].DataBlk := in_msg.DataBlk;
-      DEBUG_EXPR(in_msg.Address);
-      DEBUG_EXPR(in_msg.DataBlk);
+      DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+              in_msg.Address, in_msg.DataBlk);
     }
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index 7a234e56f..a810a3e02 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -190,13 +190,14 @@ machine(L1Cache, "Token protocol")
   int averageLatencyCounter, default="(500 << (*m_L1Cache_averageLatencyHysteresis_ptr))";
 
   int averageLatencyEstimate() {
-    DEBUG_EXPR( (averageLatencyCounter >> averageLatencyHysteresis) );
+    DPRINTF(RubySlicc, "%d\n",
+            (averageLatencyCounter >> averageLatencyHysteresis));
     //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
     return averageLatencyCounter >> averageLatencyHysteresis;
   }
 
   void updateAverageLatencyEstimate(int latency) {
-    DEBUG_EXPR( latency );
+    DPRINTF(RubySlicc, "%d\n", latency);
     assert(latency >= 0);
 
     // By subtracting the current average and then adding the most
@@ -890,8 +891,8 @@ machine(L1Cache, "Token protocol")
         // Increment IssueCount
         L1_TBEs[address].IssueCount := L1_TBEs[address].IssueCount + 1;
 
-        DEBUG_EXPR("incremented issue count");
-        DEBUG_EXPR(L1_TBEs[address].IssueCount);
+        DPRINTF(RubySlicc, "incremented issue count to %d\n",
+                L1_TBEs[address].IssueCount);
 
         // Set a wakeup timer
         if (dynamic_timeout_enabled) {
@@ -1203,8 +1204,8 @@ machine(L1Cache, "Token protocol")
 
 
   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, getCacheEntry(address).DataBlk);
 
     sequencer.readCallback(address, 
                            GenericMachineType:L1Cache, 
@@ -1213,8 +1214,8 @@ machine(L1Cache, "Token protocol")
   }
 
   action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, getCacheEntry(address).DataBlk);
     peek(responseNetwork_in, ResponseMsg) {
 
       sequencer.readCallback(address, 
@@ -1225,20 +1226,20 @@ machine(L1Cache, "Token protocol")
   }
 
   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, getCacheEntry(address).DataBlk);
 
     sequencer.writeCallback(address, 
                             GenericMachineType:L1Cache, 
                             getCacheEntry(address).DataBlk);
 
     getCacheEntry(address).Dirty := true;
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
   }
 
   action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
-    DEBUG_EXPR(address);
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+            address, getCacheEntry(address).DataBlk);
     peek(responseNetwork_in, ResponseMsg) {
 
       sequencer.writeCallback(address,
@@ -1247,7 +1248,7 @@ machine(L1Cache, "Token protocol")
 
     }
     getCacheEntry(address).Dirty := true;
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
   }
 
   action(i_allocateTBE, "i", desc="Allocate TBE") {
@@ -1317,11 +1318,10 @@ machine(L1Cache, "Token protocol")
   action(q_updateTokensFromResponse, "q", desc="Update the token count based on the incoming response message") {
     peek(responseNetwork_in, ResponseMsg) {
       assert(in_msg.Tokens != 0);
-      DEBUG_EXPR("MRM_DEBUG L1 received tokens");
-      DEBUG_EXPR(in_msg.Address);
-      DEBUG_EXPR(in_msg.Tokens);
+      DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
+              in_msg.Address, in_msg.Tokens);
       getCacheEntry(address).Tokens := getCacheEntry(address).Tokens + in_msg.Tokens;
-      DEBUG_EXPR(getCacheEntry(address).Tokens);
+      DPRINTF(RubySlicc, "%d\n", getCacheEntry(address).Tokens);
 
       if (getCacheEntry(address).Dirty == false && in_msg.Dirty) {
         getCacheEntry(address).Dirty := true;
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
index ae239e3ef..3541da41b 100644
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -311,7 +311,7 @@ machine(L2Cache, "Token protocol")
     } else if(type == CoherenceRequestType:GETX) {
       return GenericRequestType:GETX;
     } else {
-      DEBUG_EXPR(type);
+      DPRINTF(RubySlicc, "%s\n", type);
       error("invalid CoherenceRequestType");
     }
   }
@@ -475,7 +475,7 @@ machine(L2Cache, "Token protocol")
           } else if (in_msg.Type == CoherenceResponseType:INV) {
             trigger(Event:L1_INV, in_msg.Address);
           } else {
-            DEBUG_EXPR(in_msg.Type);
+            DPRINTF(RubySlicc, "%s\n", in_msg.Type);
             error("Unexpected message");
           }
         }
@@ -765,8 +765,8 @@ machine(L2Cache, "Token protocol")
     peek(requestNetwork_in, RequestMsg) {
       if (filtering_enabled == true && in_msg.RetryNum == 0 && sharersExist(in_msg.Address) == false) {
         //profile_filter_action(1);
-        DEBUG_EXPR("filtered message");
-        DEBUG_EXPR(in_msg.RetryNum);
+        DPRINTF(RubySlicc, "filtered message, Retry Num: %d\n",
+                in_msg.RetryNum);
       }
       else {
         enqueue(localRequestNetwork_out, RequestMsg, latency=l2_response_latency ) {
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index 79a3839f7..041d9b743 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -227,7 +227,7 @@ machine(Directory, "Token protocol")
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
           trigger(Event:Memory_Ack, in_msg.Address);
         } else {
-          DEBUG_EXPR(in_msg.Type);
+          DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
         }
       }
@@ -254,7 +254,7 @@ machine(Directory, "Token protocol")
           } else if (in_msg.Type == CoherenceResponseType:ACK) {
             trigger(Event:Ack_All_Tokens, in_msg.Address);
           } else {
-            DEBUG_EXPR(in_msg.Type);
+            DPRINTF(RubySlicc, "%s\n", in_msg.Type);
             error("Invalid message");
           }
         } else {
@@ -266,7 +266,7 @@ machine(Directory, "Token protocol")
           } else if (in_msg.Type == CoherenceResponseType:ACK_OWNER) {
             trigger(Event:Ack_Owner, in_msg.Address);
           } else {
-            DEBUG_EXPR(in_msg.Type);
+            DPRINTF(RubySlicc, "%s\n", in_msg.Type);
             error("Invalid message");
           }
         }
@@ -590,7 +590,7 @@ machine(Directory, "Token protocol")
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -603,7 +603,7 @@ machine(Directory, "Token protocol")
       out_msg.OriginalRequestorMachId := persistentTable.findSmallest(address);
       out_msg.MessageSize := MessageSizeType:Request_Control;
       out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
-      DEBUG_EXPR(out_msg);
+      DPRINTF(RubySlicc, "%s\n", out_msg);
     }
   }
 
@@ -616,7 +616,7 @@ machine(Directory, "Token protocol")
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -625,7 +625,7 @@ machine(Directory, "Token protocol")
     enqueue(memQueue_out, MemoryMsg, latency="1") {
       out_msg.Address := address;
       out_msg.Type := MemoryRequestType:MEMORY_WB;
-      DEBUG_EXPR(out_msg);
+      DPRINTF(RubySlicc, "%s\n", out_msg);
     }
   }
 
@@ -637,7 +637,7 @@ machine(Directory, "Token protocol")
       out_msg.DataBlk := TBEs[address].DataBlk;
       // then add the dma write data
       out_msg.DataBlk.copyPartial(TBEs[address].DmaDataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
-      DEBUG_EXPR(out_msg);
+      DPRINTF(RubySlicc, "%s\n", out_msg);
     }
   }
 
@@ -647,7 +647,7 @@ machine(Directory, "Token protocol")
       out_msg.Type := MemoryRequestType:MEMORY_WB;
       // first, initialize the data blk to the current version of system memory
       out_msg.DataBlk := TBEs[address].DataBlk;
-      DEBUG_EXPR(out_msg);
+      DPRINTF(RubySlicc, "%s\n", out_msg);
     }
   }
 
@@ -755,8 +755,8 @@ machine(Directory, "Token protocol")
   action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
     peek(responseNetwork_in, ResponseMsg) {
       getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
-      DEBUG_EXPR(in_msg.Address);
-      DEBUG_EXPR(in_msg.DataBlk);
+      DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+              in_msg.Address, in_msg.DataBlk);
     }
   }
 
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index f99194a75..02463405b 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -513,7 +513,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
         out_msg.DataBlk := getCacheEntry(address).DataBlk;
-        DEBUG_EXPR(out_msg.DataBlk);
+        DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
         out_msg.Dirty := getCacheEntry(address).Dirty;
         if (in_msg.DirectedProbe) {
           out_msg.Acks := machineCount(MachineType:L1Cache);
@@ -535,7 +535,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
         out_msg.Sender := machineID;
         out_msg.Destination := in_msg.MergedRequestors;
         out_msg.DataBlk := getCacheEntry(address).DataBlk;
-        DEBUG_EXPR(out_msg.DataBlk);
+        DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
         out_msg.Dirty := getCacheEntry(address).Dirty;
         out_msg.Acks := machineCount(MachineType:L1Cache);
         out_msg.MessageSize := MessageSizeType:Response_Data;
@@ -609,7 +609,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   }
 
   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
 
     sequencer.readCallback(address, 
                            testAndClearLocalHit(address), 
@@ -618,7 +618,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   }
 
   action(hx_external_load_hit, "hx", desc="load required external msgs") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
     peek(responseToCache_in, ResponseMsg) {
 
       sequencer.readCallback(address, 
@@ -632,7 +632,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   }
 
   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
     peek(mandatoryQueue_in, CacheMsg) {
       sequencer.writeCallback(address, 
                               testAndClearLocalHit(address), 
@@ -646,7 +646,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   }
 
   action(sx_external_store_hit, "sx", desc="store required external msgs.") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
     peek(responseToCache_in, ResponseMsg) {
 
       sequencer.writeCallback(address, 
@@ -661,7 +661,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   }
 
   action(sxt_trig_ext_store_hit, "sxt", desc="store required external msgs.") {
-    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
 
     sequencer.writeCallback(address, 
                             getNondirectHitMachType(address, 
@@ -697,9 +697,9 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
     peek(responseToCache_in, ResponseMsg) {
       assert(in_msg.Acks > 0);
-      DEBUG_EXPR(TBEs[address].NumPendingMsgs);
+      DPRINTF(RubySlicc, "%d\n", TBEs[address].NumPendingMsgs);
       TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - in_msg.Acks;
-      DEBUG_EXPR(TBEs[address].NumPendingMsgs);
+      DPRINTF(RubySlicc, "%d\n", TBEs[address].NumPendingMsgs);
       TBEs[address].LastResponder := in_msg.Sender;
       if (TBEs[address].InitialRequestTime != zero_time() && in_msg.InitialRequestTime != zero_time()) {
         assert(TBEs[address].InitialRequestTime == in_msg.InitialRequestTime);
@@ -763,7 +763,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
-        DEBUG_EXPR(out_msg.Destination);
+        DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
         out_msg.DataBlk := TBEs[address].DataBlk;
         out_msg.Dirty := TBEs[address].Dirty;
         if (in_msg.DirectedProbe) {
@@ -785,7 +785,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination := in_msg.MergedRequestors;
-        DEBUG_EXPR(out_msg.Destination);
+        DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
         out_msg.DataBlk := TBEs[address].DataBlk;
         out_msg.Dirty := TBEs[address].Dirty;
         out_msg.Acks := machineCount(MachineType:L1Cache);
@@ -854,8 +854,8 @@ machine(L1Cache, "AMD Hammer-like protocol")
 
   action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
     peek(responseToCache_in, ResponseMsg) {
-      DEBUG_EXPR(getCacheEntry(address).DataBlk);
-      DEBUG_EXPR(in_msg.DataBlk);
+      DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
+              getCacheEntry(address).DataBlk, in_msg.DataBlk);
       assert(getCacheEntry(address).DataBlk == in_msg.DataBlk);
       getCacheEntry(address).DataBlk := in_msg.DataBlk;
       getCacheEntry(address).Dirty := in_msg.Dirty || getCacheEntry(address).Dirty;
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 9f7d08f9d..e6e474e95 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -311,7 +311,7 @@ machine(Directory, "AMD Hammer-like protocol")
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
           trigger(Event:Memory_Ack, in_msg.Address);
         } else {
-          DEBUG_EXPR(in_msg.Type);
+          DPRINTF(RubySlicc, "%d\n", in_msg.Type);
           error("Invalid message");
         }
       }
@@ -483,28 +483,28 @@ machine(Directory, "AMD Hammer-like protocol")
   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
     peek(responseToDir_in, ResponseMsg) {
       assert(in_msg.Acks > 0);
-      DEBUG_EXPR(TBEs[address].NumPendingMsgs);
+      DPRINTF(RubySlicc, "%d\n", TBEs[address].NumPendingMsgs);
       //
       // Note that cache data responses will have an ack count of 2.  However, 
       // directory DMA requests must wait for acks from all LLC caches, so 
       // only decrement by 1.
       //
       TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - 1;
-      DEBUG_EXPR(TBEs[address].NumPendingMsgs);
+      DPRINTF(RubySlicc, "%d\n", TBEs[address].NumPendingMsgs);
     }
   }
 
   action(mu_decrementNumberOfUnblocks, "mu", desc="Decrement the number of messages for which we're waiting") {
     peek(unblockNetwork_in, ResponseMsg) {
       assert(in_msg.Type == CoherenceResponseType:UNBLOCKS);
-      DEBUG_EXPR(TBEs[address].NumPendingMsgs);
+      DPRINTF(RubySlicc, "%d\n", TBEs[address].NumPendingMsgs);
       //
       // Note that cache data responses will have an ack count of 2.  However, 
       // directory DMA requests must wait for acks from all LLC caches, so 
       // only decrement by 1.
       //
       TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - 1;
-      DEBUG_EXPR(TBEs[address].NumPendingMsgs);
+      DPRINTF(RubySlicc, "%d\n", TBEs[address].NumPendingMsgs);
     }
   }
 
@@ -566,10 +566,10 @@ machine(Directory, "AMD Hammer-like protocol")
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
         out_msg.DataBlk := in_msg.DataBlk;
-        DEBUG_EXPR(out_msg.DataBlk);
+        DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
         out_msg.Dirty := false; // By definition, the block is now clean
         out_msg.Acks := TBEs[address].Acks;
-        DEBUG_EXPR(out_msg.Acks);
+        DPRINTF(RubySlicc, "%d\n", out_msg.Acks);
         assert(out_msg.Acks > 0);
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
@@ -656,7 +656,7 @@ machine(Directory, "AMD Hammer-like protocol")
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -670,7 +670,7 @@ machine(Directory, "AMD Hammer-like protocol")
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -876,8 +876,8 @@ machine(Directory, "AMD Hammer-like protocol")
   action(wr_writeResponseDataToMemory, "wr", desc="Write response data to memory") {
     peek(responseToDir_in, ResponseMsg) {
       getDirectoryEntry(address).DataBlk := in_msg.DataBlk;
-      DEBUG_EXPR(in_msg.Address);
-      DEBUG_EXPR(in_msg.DataBlk);
+      DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+              in_msg.Address, in_msg.DataBlk);
     }
   }
 
@@ -886,23 +886,23 @@ machine(Directory, "AMD Hammer-like protocol")
       assert(in_msg.Dirty);
       assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
       getDirectoryEntry(address).DataBlk := in_msg.DataBlk;
-      DEBUG_EXPR(in_msg.Address);
-      DEBUG_EXPR(in_msg.DataBlk);
+      DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+              in_msg.Address, in_msg.DataBlk);
     }
   }
 
   action(dwt_writeDmaDataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
-    DEBUG_EXPR(getDirectoryEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
     getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
-    DEBUG_EXPR(getDirectoryEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
     getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DmaDataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
-    DEBUG_EXPR(getDirectoryEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
   }
 
   action(wdt_writeDataFromTBE, "wdt", desc="DMA Write data to memory from TBE") {
-    DEBUG_EXPR(getDirectoryEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
     getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
-    DEBUG_EXPR(getDirectoryEntry(address).DataBlk);
+    DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
   }
 
   action(a_assertCacheData, "ac", desc="Assert that a cache provided the data") {
@@ -922,7 +922,7 @@ machine(Directory, "AMD Hammer-like protocol")
       enqueue(memQueue_out, MemoryMsg, latency="1") {
         out_msg.Address := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
-        DEBUG_EXPR(out_msg);
+        DPRINTF(RubySlicc, "%s\n", out_msg);
       }
     }
   }
@@ -935,7 +935,7 @@ machine(Directory, "AMD Hammer-like protocol")
       out_msg.DataBlk := TBEs[address].DataBlk;
       // then add the dma write data
       out_msg.DataBlk.copyPartial(TBEs[address].DmaDataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
-      DEBUG_EXPR(out_msg);
+      DPRINTF(RubySlicc, "%s\n", out_msg);
     }
   }