ruby: MI_example updates to use the new config system

4 files changed, 50 insertions, 70 deletions

diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 2f637e7b7..725ce0ec3 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -1,7 +1,9 @@
 
 machine(L1Cache, "MI Example L1 Cache")
-: int cache_response_latency,
-  int issue_latency
+: Sequencer * sequencer,
+  CacheMemory * cacheMemory,
+  int cache_response_latency = 12,
+  int issue_latency = 2
 {
 
   // NETWORK BUFFERS
@@ -44,7 +46,6 @@ machine(L1Cache, "MI Example L1 Cache")
   // STRUCTURE DEFINITIONS
 
   MessageBuffer mandatoryQueue, ordered="false";
-  Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])';
 
   // CacheEntry
   structure(Entry, desc="...", interface="AbstractCacheEntry") {
@@ -54,17 +55,6 @@ machine(L1Cache, "MI Example L1 Cache")
   }
 
 
-  external_type(CacheMemory) {
-    bool cacheAvail(Address);
-    Address cacheProbe(Address);
-    void allocate(Address, Entry);
-    void deallocate(Address);
-    Entry lookup(Address);
-    void changePermission(Address, AccessPermission);
-    bool isTagPresent(Address);
-    void profileMiss(CacheMsg);
-  }
-
   // TBE fields
   structure(TBE, desc="...") {
     State TBEState,          desc="Transient state";
@@ -81,8 +71,6 @@ machine(L1Cache, "MI Example L1 Cache")
 
   // STRUCTURES
 
-  CacheMemory cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])';
-
   TBETable TBEs, template_hack="<L1Cache_TBE>";
 
 
@@ -100,6 +88,9 @@ machine(L1Cache, "MI Example L1 Cache")
     }
   }
 
+  Entry getCacheEntry(Address addr), return_by_ref="yes" {
+    return static_cast(Entry, cacheMemory[addr]);
+  }
 
   State getState(Address addr) {
 
@@ -107,7 +98,7 @@ machine(L1Cache, "MI Example L1 Cache")
       return TBEs[addr].TBEState;
     }
     else if (cacheMemory.isTagPresent(addr)) {
-      return cacheMemory[addr].CacheState;
+      return getCacheEntry(addr).CacheState;
     }
     else {
       return State:I;
@@ -121,7 +112,7 @@ machine(L1Cache, "MI Example L1 Cache")
     }
 
     if (cacheMemory.isTagPresent(addr)) {
-      cacheMemory[addr].CacheState := state;
+      getCacheEntry(addr).CacheState := state;
       if (state == State:M) {
         cacheMemory.changePermission(addr, AccessPermission:Read_Write);
       } else {
@@ -207,7 +198,7 @@ machine(L1Cache, "MI Example L1 Cache")
       out_msg.Type := CoherenceRequestType:PUTX;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
-      out_msg.DataBlk := cacheMemory[address].DataBlk;
+      out_msg.DataBlk := getCacheEntry(address).DataBlk;
       out_msg.MessageSize := MessageSizeType:Data;
     }
   }
@@ -220,7 +211,7 @@ machine(L1Cache, "MI Example L1 Cache")
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
-        out_msg.DataBlk := cacheMemory[address].DataBlk;
+        out_msg.DataBlk := getCacheEntry(address).DataBlk;
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
     }
@@ -271,19 +262,19 @@ machine(L1Cache, "MI Example L1 Cache")
   }
 
   action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
-    DEBUG_EXPR(cacheMemory[address].DataBlk);
-    sequencer.readCallback(address, cacheMemory[address].DataBlk);
+    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    sequencer.readCallback(address, getCacheEntry(address).DataBlk);
   }
 
   action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
-    DEBUG_EXPR(cacheMemory[address].DataBlk);
-    sequencer.writeCallback(address, cacheMemory[address].DataBlk);
+    DEBUG_EXPR(getCacheEntry(address).DataBlk);
+    sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
   }
 
 
   action(u_writeDataToCache, "u", desc="Write data to the cache") {
     peek(responseNetwork_in, ResponseMsg) {
-      cacheMemory[address].DataBlk := in_msg.DataBlk;
+      getCacheEntry(address).DataBlk := in_msg.DataBlk;
     }
   }
 
@@ -298,7 +289,7 @@ machine(L1Cache, "MI Example L1 Cache")
   }
 
   action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
-    TBEs[address].DataBlk := cacheMemory[address].DataBlk;
+    TBEs[address].DataBlk := getCacheEntry(address).DataBlk;
   }
 
   action(z_stall, "z", desc="stall") {
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index 1f64d25df..12f7e4552 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -1,6 +1,8 @@
 
 machine(Directory, "Directory protocol") 
-: int directory_latency
+: DirectoryMemory * directory,
+  MemoryControl * memBuffer,
+  int directory_latency = 12
 {
 
   MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
@@ -48,24 +50,13 @@ machine(Directory, "Directory protocol")
   // TYPES
 
   // DirectoryEntry
-  structure(Entry, desc="...") {
+  structure(Entry, desc="...", interface="AbstractEntry") {
     State DirectoryState,          desc="Directory state";
     DataBlock DataBlk,             desc="data for the block";
     NetDest Sharers,                   desc="Sharers for this block";
     NetDest Owner,                     desc="Owner of this block";
   }
 
-  external_type(DirectoryMemory) {
-    Entry lookup(Address);
-    bool isPresent(Address);
-    void invalidateBlock(Address);
-  }
-
-  external_type(MemoryControl, inport="yes", outport="yes") {
-
-  }
-
-
   // TBE entries for DMA requests
   structure(TBE, desc="TBE entries for outstanding DMA requests") {
     Address PhysicalAddress, desc="physical address";
@@ -83,17 +74,17 @@ machine(Directory, "Directory protocol")
   }
 
   // ** OBJECTS **
-  DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory"])';
-
-  MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_control"])';
-
   TBETable TBEs, template_hack="<Directory_TBE>";
 
+  Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
+    return static_cast(Entry, directory[addr]);
+  }
+ 
   State getState(Address addr) {
     if (TBEs.isPresent(addr)) {
       return TBEs[addr].TBEState;
     } else if (directory.isPresent(addr)) {
-      return directory[addr].DirectoryState;
+      return getDirectoryEntry(addr).DirectoryState;
     } else {
       return State:I;
     }
@@ -108,14 +99,14 @@ machine(Directory, "Directory protocol")
     if (directory.isPresent(addr)) {
 
       if (state == State:I)  {
-        assert(directory[addr].Owner.count() == 0);
-        assert(directory[addr].Sharers.count() == 0);
+        assert(getDirectoryEntry(addr).Owner.count() == 0);
+        assert(getDirectoryEntry(addr).Sharers.count() == 0);
       } else if (state == State:M) {
-        assert(directory[addr].Owner.count() == 1);
-        assert(directory[addr].Sharers.count() == 0);
+        assert(getDirectoryEntry(addr).Owner.count() == 1);
+        assert(getDirectoryEntry(addr).Sharers.count() == 0);
       }
 
-      directory[addr].DirectoryState := state;
+      getDirectoryEntry(addr).DirectoryState := state;
     }
   }
 
@@ -151,7 +142,7 @@ machine(Directory, "Directory protocol")
         } else if (in_msg.Type == CoherenceRequestType:GETX) {
           trigger(Event:GETX, in_msg.Address);
         } else if (in_msg.Type == CoherenceRequestType:PUTX) {
-          if (directory[in_msg.Address].Owner.isElement(in_msg.Requestor)) {
+          if (getDirectoryEntry(in_msg.Address).Owner.isElement(in_msg.Requestor)) {
             trigger(Event:PUTX, in_msg.Address);
           } else {
             trigger(Event:PUTX_NotOwner, in_msg.Address);
@@ -219,7 +210,7 @@ machine(Directory, "Directory protocol")
   }
 
   action(c_clearOwner, "c", desc="Clear the owner field") {
-    directory[address].Owner.clear();
+    getDirectoryEntry(address).Owner.clear();
   }
 
   action(d_sendData, "d", desc="Send data to requestor") {
@@ -279,22 +270,22 @@ machine(Directory, "Directory protocol")
 
   action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
     peek(requestQueue_in, RequestMsg) {
-      directory[address].Owner.clear();
-      directory[address].Owner.add(in_msg.Requestor);
+      getDirectoryEntry(address).Owner.clear();
+      getDirectoryEntry(address).Owner.add(in_msg.Requestor);
     }
   }
 
   action(f_forwardRequest, "f", desc="Forward request to owner") {
     peek(requestQueue_in, RequestMsg) {
       APPEND_TRANSITION_COMMENT("Own: ");
-      APPEND_TRANSITION_COMMENT(directory[in_msg.Address].Owner);
+      APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.Address).Owner);
       APPEND_TRANSITION_COMMENT("Req: ");
       APPEND_TRANSITION_COMMENT(in_msg.Requestor);
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
         out_msg.Address := address;
         out_msg.Type := in_msg.Type;
         out_msg.Requestor := in_msg.Requestor;
-        out_msg.Destination := directory[in_msg.Address].Owner;
+        out_msg.Destination := getDirectoryEntry(in_msg.Address).Owner;
         out_msg.MessageSize := MessageSizeType:Writeback_Control;
       }
     }
@@ -306,7 +297,7 @@ machine(Directory, "Directory protocol")
         out_msg.Address := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := machineID;
-        out_msg.Destination := directory[in_msg.PhysicalAddress].Owner;
+        out_msg.Destination := getDirectoryEntry(in_msg.PhysicalAddress).Owner;
         out_msg.MessageSize := MessageSizeType:Writeback_Control;
       }
     }
@@ -324,13 +315,13 @@ machine(Directory, "Directory protocol")
     peek(requestQueue_in, RequestMsg) {
       // assert(in_msg.Dirty);
       // assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
-      directory[in_msg.Address].DataBlk := in_msg.DataBlk;
-      //directory[in_msg.Address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
+      getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
+      //getDirectoryEntry(in_msg.Address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
     }
   }
   
   action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
-    directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
+    getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
   }
 
   action(v_allocateTBE, "v", desc="Allocate TBE") {
@@ -378,7 +369,7 @@ machine(Directory, "Directory protocol")
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
-        out_msg.DataBlk := directory[in_msg.Address].DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
         DEBUG_EXPR(out_msg);
       }
     }
@@ -392,7 +383,7 @@ machine(Directory, "Directory protocol")
         out_msg.Sender := machineID;
         //out_msg.OriginalRequestorMachId := machineID;
         out_msg.MessageSize := in_msg.MessageSize;
-        out_msg.DataBlk := directory[address].DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
         DEBUG_EXPR(out_msg);
       }
     }
@@ -453,8 +444,10 @@ machine(Directory, "Directory protocol")
   }
 
   action(w_writeDataToMemoryFromTBE, "\w", desc="Write date to directory memory from TBE") {
-    //directory[address].DataBlk := TBEs[address].DataBlk;
-    directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
+    //getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
+    getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk, 
+                                addressOffset(TBEs[address].PhysicalAddress), 
+                                TBEs[address].Len);
 
   }
 
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index 79c42e719..17060dd4d 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -1,6 +1,7 @@
 
 machine(DMA, "DMA Controller") 
-: int request_latency
+: DMASequencer * dma_sequencer,
+  int request_latency
 {
 
   MessageBuffer responseFromDir, network="From", virtual_network="4", ordered="true", no_vector="true";
@@ -19,13 +20,7 @@ machine(DMA, "DMA Controller")
     Ack,          desc="DMA write to memory completed";
   }
 
-  external_type(DMASequencer) {
-    void ackCallback();
-    void dataCallback(DataBlock);
-  }
-
   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
   State cur_state, no_vector="true";
 
   State getState(Address addr) {
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 10e3711c5..a724b25da 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -103,6 +103,7 @@ external_type(AbstractEntry, primitive="yes");
 external_type(DirectoryMemory) {
   AbstractEntry lookup(Address);
   bool isPresent(Address);
+  void invalidateBlock(Address);
 }
 
 external_type(AbstractCacheEntry, primitive="yes");