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| author | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
|---|---|---|
| committer | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
| commit | 7e9562013b1592c5cc402c43ee1d21025f375a71 (patch) | |
| tree | 3e14882024790d898404eb246d37fa51051c4f8f /src/mem/protocol | |
| parent | 7e00772bda1a1c74fe659c56fea803642302c1da (diff) | |
| download | gem5-7e9562013b1592c5cc402c43ee1d21025f375a71.tar.xz | |
ruby: allocate a block in CacheMemory without updating LRU state
Diffstat (limited to 'src/mem/protocol')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Types.sm | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index 51f99b603..6c3c4168d 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -146,6 +146,7 @@ structure (CacheMemory, external = "yes") { bool cacheAvail(Address); Address cacheProbe(Address); AbstractCacheEntry allocate(Address, AbstractCacheEntry); + AbstractCacheEntry allocate(Address, AbstractCacheEntry, bool); void allocateVoid(Address, AbstractCacheEntry); void deallocate(Address); AbstractCacheEntry lookup(Address); |