ruby: MESI_CMP_directory updated to the new config system

4 files changed, 57 insertions, 105 deletions

diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index 39ede67ca..57a147900 100644
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -28,11 +28,13 @@
  */
 
 machine(L1Cache, "MSI Directory L1 Cache CMP")
- : int l1_request_latency,
-   int l1_response_latency,
-   int to_l2_latency,
-   int l2_select_low_bit,
-   int l2_select_num_bits
+ : Sequencer * sequencer,
+   CacheMemory * L1IcacheMemory,
+   CacheMemory * L1DcacheMemory,
+   int l2_select_num_bits,
+   int l1_request_latency = 2,
+   int l1_response_latency = 2,
+   int to_l2_latency = 1
 {
 
 
@@ -118,16 +120,6 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
     int pendingAcks, default="0", desc="number of pending acks";
   }
 
-  external_type(CacheMemory) {
-    bool cacheAvail(Address);
-    Address cacheProbe(Address);
-    void allocate(Address, Entry);
-    void deallocate(Address);
-    Entry lookup(Address);
-    void changePermission(Address, AccessPermission);
-    bool isTagPresent(Address);
-  }
-
   external_type(TBETable) {
     TBE lookup(Address);
     void allocate(Address);
@@ -137,30 +129,17 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
 
   TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
 
-//  CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"', abstract_chip_ptr="true";
-//  CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"', abstract_chip_ptr="true";
-
-  CacheMemory L1IcacheMemory, factory='RubySystem::getCache(m_cfg["icache"])';
-
-  CacheMemory L1DcacheMemory, factory='RubySystem::getCache(m_cfg["dcache"])';
-
-
-//  MessageBuffer mandatoryQueue, ordered="false", rank="100", abstract_chip_ptr="true";
-
-//  Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
-
   MessageBuffer mandatoryQueue, ordered="false";
-  Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])';
-
 
   int cache_state_to_int(State state);
+  int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   // inclusive cache returns L1 entries only
   Entry getL1CacheEntry(Address addr), return_by_ref="yes" {
     if (L1DcacheMemory.isTagPresent(addr)) {
-      return L1DcacheMemory[addr];
+      return static_cast(Entry, L1DcacheMemory[addr]);
     } else {
-      return L1IcacheMemory[addr];
+      return static_cast(Entry, L1IcacheMemory[addr]);
     }
   }
 
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index b82d77ddb..e7877211a 100644
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -33,9 +33,10 @@
  */
 
 machine(L2Cache, "MESI Directory L2 Cache CMP")
- : int l2_request_latency,  
-   int l2_response_latency,
-   int to_l1_latency
+ : CacheMemory * L2cacheMemory,
+   int l2_request_latency = 2,  
+   int l2_response_latency = 2,
+   int to_l1_latency = 1
 {
 
   // L2 BANK QUEUES
@@ -145,17 +146,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     int pendingAcks,            desc="number of pending acks for invalidates during writeback";
   }
 
-  external_type(CacheMemory) {
-    bool cacheAvail(Address);
-    Address cacheProbe(Address);
-    void allocate(Address, Entry);
-    void deallocate(Address);
-    Entry lookup(Address);
-    void changePermission(Address, AccessPermission);
-    bool isTagPresent(Address);
-    void setMRU(Address);
-  }
-
   external_type(TBETable) {
     TBE lookup(Address);
     void allocate(Address);
@@ -165,14 +155,9 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
 
   TBETable L2_TBEs, template_hack="<L2Cache_TBE>";
 
-//  CacheMemory L2cacheMemory, template_hack="<L2Cache_Entry>", constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L2Cache,int_to_string(i)';
-
-
-  CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])';
-
   // inclusive cache, returns L2 entries only
   Entry getL2CacheEntry(Address addr), return_by_ref="yes" {
-    return L2cacheMemory[addr];
+    return static_cast(Entry, L2cacheMemory[addr]);
   }
 
   void changeL2Permission(Address addr, AccessPermission permission) {
@@ -190,13 +175,13 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   }
 
   bool isOneSharerLeft(Address addr, MachineID requestor) {
-    assert(L2cacheMemory[addr].Sharers.isElement(requestor));
-    return (L2cacheMemory[addr].Sharers.count() == 1);
+    assert(getL2CacheEntry(addr).Sharers.isElement(requestor));
+    return (getL2CacheEntry(addr).Sharers.count() == 1);
   }
 
   bool isSharer(Address addr, MachineID requestor) {
     if (L2cacheMemory.isTagPresent(addr)) {
-      return L2cacheMemory[addr].Sharers.isElement(requestor);
+      return getL2CacheEntry(addr).Sharers.isElement(requestor);
     } else {
       return false;
     }
@@ -206,7 +191,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     //DEBUG_EXPR(machineID);
     //DEBUG_EXPR(requestor);
     //DEBUG_EXPR(addr);
-    L2cacheMemory[addr].Sharers.add(requestor);
+    getL2CacheEntry(addr).Sharers.add(requestor);
   }
 
   State getState(Address addr) {
@@ -361,7 +346,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
             trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address, in_msg.Requestor), in_msg.Address);
           } else {
             // No room in the L2, so we need to make room before handling the request
-            if (L2cacheMemory[ L2cacheMemory.cacheProbe(in_msg.Address) ].Dirty ) {
+            if (getL2CacheEntry( L2cacheMemory.cacheProbe(in_msg.Address) ).Dirty ) {
               trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
             } else {
               trigger(Event:L2_Replacement_clean, L2cacheMemory.cacheProbe(in_msg.Address));
@@ -393,7 +378,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
         out_msg.Address := address;
         out_msg.Type := in_msg.Type;
         out_msg.Requestor := in_msg.Requestor;
-        out_msg.Destination.add(L2cacheMemory[address].Exclusive);
+        out_msg.Destination.add(getL2CacheEntry(address).Exclusive);
         out_msg.MessageSize := MessageSizeType:Request_Control;
       }
     }
@@ -537,7 +522,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
       out_msg.Address := address;
       out_msg.Type := CoherenceRequestType:INV;
       out_msg.Requestor := machineID;
-      out_msg.Destination := L2cacheMemory[address].Sharers;
+      out_msg.Destination := getL2CacheEntry(address).Sharers;
       out_msg.MessageSize := MessageSizeType:Request_Control;
     }
   }
@@ -548,7 +533,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
         out_msg.Address := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := in_msg.Requestor;
-        out_msg.Destination := L2cacheMemory[address].Sharers;
+        out_msg.Destination := getL2CacheEntry(address).Sharers;
         out_msg.MessageSize := MessageSizeType:Request_Control;
       }
     }
@@ -561,7 +546,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
         out_msg.Address := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := in_msg.Requestor;
-        out_msg.Destination := L2cacheMemory[address].Sharers;
+        out_msg.Destination := getL2CacheEntry(address).Sharers;
         out_msg.Destination.remove(in_msg.Requestor);
         out_msg.MessageSize := MessageSizeType:Request_Control;
       }
@@ -713,28 +698,28 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
 
   action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
-      L2cacheMemory[address].Sharers.remove(in_msg.Requestor);
+      getL2CacheEntry(address).Sharers.remove(in_msg.Requestor);
     }
   }
 
   action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
-      L2cacheMemory[address].Sharers.clear();
+      getL2CacheEntry(address).Sharers.clear();
     }
   }
 
   action(mm_markExclusive, "\m", desc="set the exclusive owner") {
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
-      L2cacheMemory[address].Sharers.clear();
-      L2cacheMemory[address].Exclusive := in_msg.Requestor;
+      getL2CacheEntry(address).Sharers.clear();
+      getL2CacheEntry(address).Exclusive := in_msg.Requestor;
       addSharer(address, in_msg.Requestor);
     }
   }
 
   action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
     peek(L1unblockNetwork_in, ResponseMsg) {
-      L2cacheMemory[address].Sharers.clear();
-      L2cacheMemory[address].Exclusive := in_msg.Sender;
+      getL2CacheEntry(address).Sharers.clear();
+      getL2CacheEntry(address).Exclusive := in_msg.Sender;
       addSharer(address, in_msg.Sender);
     }
   }
diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm
index 7e30883b0..ceba6c425 100644
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm
@@ -36,8 +36,10 @@
 
 
 machine(Directory, "MESI_CMP_filter_directory protocol") 
- : int to_mem_ctrl_latency,
-   int directory_latency
+ : DirectoryMemory * directory,
+   MemoryControl * memBuffer,
+   int to_mem_ctrl_latency = 1,
+   int directory_latency = 6
 {
 
   MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false";
@@ -78,23 +80,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   // TYPES
 
   // DirectoryEntry
-  structure(Entry, desc="...") {
+  structure(Entry, desc="...", interface="AbstractEntry") {
     State DirectoryState,          desc="Directory state";
     DataBlock DataBlk,             desc="data for the block";
     NetDest Sharers,                   desc="Sharers for this block";
     NetDest Owner,                     desc="Owner of this block"; 
   }
 
-  external_type(DirectoryMemory) {
-    Entry lookup(Address);
-    bool isPresent(Address);
-  }
-
-  // to simulate detailed DRAM
-  external_type(MemoryControl, inport="yes", outport="yes") {
-
-  }
-
   // TBE entries for DMA requests
   structure(TBE, desc="TBE entries for outstanding DMA requests") {
     Address PhysicalAddress, desc="physical address";
@@ -113,21 +105,17 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   // ** OBJECTS **
 
-//  DirectoryMemory directory, constructor_hack="i";
-//  MemoryControl memBuffer, constructor_hack="i";
-
-  DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory"])';
-
-  MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_control"])';
-
-
   TBETable TBEs, template_hack="<Directory_TBE>";
       
+  Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
+    return static_cast(Entry, directory[addr]);
+  }
+
   State getState(Address addr) {
     if (TBEs.isPresent(addr)) {
       return TBEs[addr].TBEState;   
     } else if (directory.isPresent(addr)) {
-      return directory[addr].DirectoryState;
+      return getDirectoryEntry(addr).DirectoryState;
     } else {
       return State:I;
     }
@@ -143,14 +131,14 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
     if (directory.isPresent(addr)) {
   
       if (state == State:I)  {
-        assert(directory[addr].Owner.count() == 0);
-        assert(directory[addr].Sharers.count() == 0);
+        assert(getDirectoryEntry(addr).Owner.count() == 0);
+        assert(getDirectoryEntry(addr).Sharers.count() == 0);
       } else if (state == State:M) {
-        assert(directory[addr].Owner.count() == 1);
-        assert(directory[addr].Sharers.count() == 0);
+        assert(getDirectoryEntry(addr).Owner.count() == 1);
+        assert(getDirectoryEntry(addr).Sharers.count() == 0);
       }
       
-      directory[addr].DirectoryState := state;
+      getDirectoryEntry(addr).DirectoryState := state;
     }
   }
 
@@ -281,7 +269,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.Prefetch := in_msg.Prefetch;
-        out_msg.DataBlk := directory[in_msg.Address].DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
 
         DEBUG_EXPR(out_msg);
       }
@@ -306,7 +294,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
     peek(responseNetwork_in, ResponseMsg) {
-      directory[in_msg.Address].DataBlk := in_msg.DataBlk;
+      getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
       DEBUG_EXPR(in_msg.Address);
       DEBUG_EXPR(in_msg.DataBlk);
     }
@@ -320,7 +308,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := machineID;
         out_msg.MessageSize := in_msg.MessageSize;
-        out_msg.DataBlk := directory[address].DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
         DEBUG_EXPR(out_msg);
       }
     }
@@ -344,7 +332,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
     peek(requestNetwork_in, RequestMsg) {
-      directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
+      getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
     }
   }
 
@@ -386,8 +374,8 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
     peek(requestNetwork_in, RequestMsg) {
-      directory[address].Owner.clear();
-      directory[address].Owner.add(in_msg.Requestor);
+      getDirectoryEntry(address).Owner.clear();
+      getDirectoryEntry(address).Owner.add(in_msg.Requestor);
     }
   }
 
@@ -398,7 +386,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
       out_msg.Address := address;
       out_msg.Type := CoherenceResponseType:INV;
       out_msg.Sender := machineID;
-      out_msg.Destination := directory[address].Owner;
+      out_msg.Destination := getDirectoryEntry(address).Owner;
       out_msg.MessageSize := MessageSizeType:Response_Control;
       }
     }
@@ -418,7 +406,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   }
 
   action(c_clearOwner, "c", desc="Clear the owner field") {
-    directory[address].Owner.clear();
+    getDirectoryEntry(address).Owner.clear();
   }
 
   action(v_allocateTBE, "v", desc="Allocate TBE") {
@@ -431,8 +419,8 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   }
 
   action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
-    //directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, TBEs[address].Offset, TBEs[address].Len);
-    directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
+    //getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk, TBEs[address].Offset, TBEs[address].Len);
+    getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
 
 
   }
diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm
index a565c8721..fe1cd2fb4 100644
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm
@@ -1,6 +1,7 @@
 
 machine(DMA, "DMA Controller") 
-: int request_latency
+: DMASequencer * dma_sequencer,
+  int request_latency = 6
 {
 
   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
@@ -25,7 +26,6 @@ machine(DMA, "DMA Controller")
   }
 
   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
   State cur_state, no_vector="true";
 
   State getState(Address addr) {