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author | Pouya Fotouhi <Pouya.Fotouhi@amd.com> | 2019-08-07 20:05:49 -0500 |
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committer | Pouya Fotouhi <pfotouhi@ucdavis.edu> | 2019-08-13 00:52:05 +0000 |
commit | 8b4f2ca9023ef32b8d2b076502cbe90b35b70b4e (patch) | |
tree | cd60b0c056bee8b92363b0df341edce354edc839 /src/mem/protocol | |
parent | 4651f361935415c3785520ec213698483ab24975 (diff) | |
download | gem5-8b4f2ca9023ef32b8d2b076502cbe90b35b70b4e.tar.xz |
mem-ruby: Use check_on_cache_probe on MOESI CMP
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MOESI CMP.
Change-Id: I3a8879e10ebd94ef68194836475e656761fed62c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19908
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/protocol')
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 1f573162b..b8d8ab4a0 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -412,10 +412,13 @@ machine(MachineType:L1Cache, "L1 cache protocol") TBEs[in_msg.LineAddress]); } else { // No room in the L1, so we need to make room in the L1 + // Check if the line we want to evict is not locked + Addr addr := L1Icache.cacheProbe(in_msg.LineAddress); + check_on_cache_probe(mandatoryQueue_in, addr); trigger(Event:L1_Replacement, - L1Icache.cacheProbe(in_msg.LineAddress), - getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)), - TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]); + addr, + getL1ICacheEntry(addr), + TBEs[addr]); } } } else { @@ -443,10 +446,13 @@ machine(MachineType:L1Cache, "L1 cache protocol") TBEs[in_msg.LineAddress]); } else { // No room in the L1, so we need to make room in the L1 + // Check if the line we want to evict is not locked + Addr addr := L1Dcache.cacheProbe(in_msg.LineAddress); + check_on_cache_probe(mandatoryQueue_in, addr); trigger(Event:L1_Replacement, - L1Dcache.cacheProbe(in_msg.LineAddress), - getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)), - TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]); + addr, + getL1DCacheEntry(addr), + TBEs[addr]); } } } |