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| author | Pouya Fotouhi <Pouya.Fotouhi@amd.com> | 2019-08-07 20:11:26 -0500 |
|---|---|---|
| committer | Pouya Fotouhi <pfotouhi@ucdavis.edu> | 2019-08-13 00:52:16 +0000 |
| commit | def0a4c6fdefd9458bc15ccf7c36efdd79204821 (patch) | |
| tree | c4df06f5db877730def1f8ffb1bbfcd74290002e /src/mem/protocol | |
| parent | 8b4f2ca9023ef32b8d2b076502cbe90b35b70b4e (diff) | |
| download | gem5-def0a4c6fdefd9458bc15ccf7c36efdd79204821.tar.xz | |
mem-ruby: Use check_on_cache_probe on MOESI hammer
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MOESI hammer.
Change-Id: I2c43f22aba5af3a57e54b1c435e5d3fbba86d1d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19891
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/protocol')
| -rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 9cbd277d4..4086f42a8 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -468,7 +468,9 @@ machine(MachineType:L1Cache, "AMD Hammer-like protocol") } } else { // No room in the L1, so we need to make room + // Check if the line we want to evict is not locked Addr l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress); + check_on_cache_probe(mandatoryQueue_in, l1i_victim_addr); if (L2cache.cacheAvail(l1i_victim_addr)) { // The L2 has room, so we move the line from the L1 to the L2 trigger(Event:L1_to_L2, @@ -525,7 +527,9 @@ machine(MachineType:L1Cache, "AMD Hammer-like protocol") } } else { // No room in the L1, so we need to make room + // Check if the line we want to evict is not locked Addr l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress); + check_on_cache_probe(mandatoryQueue_in, l1i_victim_addr); if (L2cache.cacheAvail(l1d_victim_addr)) { // The L2 has room, so we move the line from the L1 to the L2 trigger(Event:L1_to_L2, |