mem: Convert DRAM controller to new-style stats

Note that this changes the stat format used by the DRAM
controller. Previously, it would have a structure looking a bit like
this:

  - system
    - dram: Main DRAM controller
    - dram_0: Rank 0
    - dram_1: Rank 1

This structure can't be replicated with new-world stats since stats
are confined to the SimObject name space. This means that the new
structure looks like this:

  - system
    - dram: Main DRAM controller
      - rank0: Rank 0
      - rank1: Rank 1

Change-Id: I7435cfaf137c94b0c18de619d816362dd0da8125
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21142
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>

1 files changed, 30 insertions, 21 deletions

diff --git a/src/mem/qos/mem_ctrl.hh b/src/mem/qos/mem_ctrl.hh
index db85f276d..e31f21b23 100644
--- a/src/mem/qos/mem_ctrl.hh
+++ b/src/mem/qos/mem_ctrl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -123,26 +123,35 @@ class MemCtrl: public AbstractMemory
     /** bus state for next request event triggered */
     BusState busStateNext;
 
-    /** per-master average QoS priority */
-    Stats::VectorStandardDeviation avgPriority;
-    /** per-master average QoS distance between assigned and queued values */
-    Stats::VectorStandardDeviation avgPriorityDistance;
-
-    /** per-priority minimum latency */
-    Stats::Vector priorityMinLatency;
-    /** per-priority maximum latency */
-    Stats::Vector priorityMaxLatency;
-    /** Count the number of turnarounds READ to WRITE */
-    Stats::Scalar numReadWriteTurnArounds;
-    /** Count the number of turnarounds WRITE to READ */
-    Stats::Scalar numWriteReadTurnArounds;
-    /** Count the number of times bus staying in READ state */
-    Stats::Scalar numStayReadState;
-    /** Count the number of times bus staying in WRITE state */
-    Stats::Scalar numStayWriteState;
-
-    /** registers statistics */
-    void regStats() override;
+    struct MemCtrlStats : public Stats::Group
+    {
+        MemCtrlStats(MemCtrl &mc);
+
+        void regStats() override;
+
+        const MemCtrl &memCtrl;
+
+        /** per-master average QoS priority */
+        Stats::VectorStandardDeviation avgPriority;
+        /**
+         * per-master average QoS distance between assigned and
+         * queued values
+         */
+        Stats::VectorStandardDeviation avgPriorityDistance;
+
+        /** per-priority minimum latency */
+        Stats::Vector priorityMinLatency;
+        /** per-priority maximum latency */
+        Stats::Vector priorityMaxLatency;
+        /** Count the number of turnarounds READ to WRITE */
+        Stats::Scalar numReadWriteTurnArounds;
+        /** Count the number of turnarounds WRITE to READ */
+        Stats::Scalar numWriteReadTurnArounds;
+        /** Count the number of times bus staying in READ state */
+        Stats::Scalar numStayReadState;
+        /** Count the number of times bus staying in WRITE state */
+        Stats::Scalar numStayWriteState;
+    } stats;
 
     /**
      * Initializes dynamically counters and