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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-11-27 16:55:50 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2019-01-17 11:09:41 +0000 |
| commit | ccc50b7355fa9964c6da3ca1de2b3c48b7728bae (patch) | |
| tree | 42efb7a18e24b092dd26f80ab4716e2ea581164f /src/mem/qos/mem_sink.cc | |
| parent | 1e9f65343c79b2c3b081e785cfec070d25292be7 (diff) | |
| download | gem5-ccc50b7355fa9964c6da3ca1de2b3c48b7728bae.tar.xz | |
mem: Determine if a packet queue forces ordering at construction
A packet queue is typically used to hold on to packets that are
schedules to be sent in the future or when they need to queue behind
younger packets that have been sent out yet. Due to memory order
requirements, some MemObjects need to maintain the order for packet
(mostly responses) that reference the same cache block.
Prior to this patch the ordering requirements where determined when
the packet was scheduled to be sent. This patch moves the parameter to
the constructor.
Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15555
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/qos/mem_sink.cc')
| -rw-r--r-- | src/mem/qos/mem_sink.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc index a951daee2..77cfbaf22 100644 --- a/src/mem/qos/mem_sink.cc +++ b/src/mem/qos/mem_sink.cc @@ -289,7 +289,7 @@ MemSinkCtrl::processNextReqEvent() removed_entries, responseLatency); // Schedule the response - port.schedTimingResp(pkt, curTick() + responseLatency, true); + port.schedTimingResp(pkt, curTick() + responseLatency); DPRINTF(QOS, "%s response scheduled at time %d\n", __func__, curTick() + responseLatency); @@ -344,7 +344,7 @@ MemSinkCtrl::regStats() MemSinkCtrl::MemoryPort::MemoryPort(const std::string& n, MemSinkCtrl& m) - : QueuedSlavePort(n, &m, queue), memory(m), queue(memory, *this) + : QueuedSlavePort(n, &m, queue, true), memory(m), queue(memory, *this, true) {} AddrRangeList |