mem: Convert DRAM controller to new-style stats

Note that this changes the stat format used by the DRAM
controller. Previously, it would have a structure looking a bit like
this:

  - system
    - dram: Main DRAM controller
    - dram_0: Rank 0
    - dram_1: Rank 1

This structure can't be replicated with new-world stats since stats
are confined to the SimObject name space. This means that the new
structure looks like this:

  - system
    - dram: Main DRAM controller
      - rank0: Rank 0
      - rank1: Rank 1

Change-Id: I7435cfaf137c94b0c18de619d816362dd0da8125
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21142
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>

2 files changed, 99 insertions, 70 deletions

diff --git a/src/mem/qos/mem_ctrl.cc b/src/mem/qos/mem_ctrl.cc
index 27ff0eb61..5ced58ae8 100644
--- a/src/mem/qos/mem_ctrl.cc
+++ b/src/mem/qos/mem_ctrl.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018 ARM Limited
+ * Copyright (c) 2017-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -52,7 +52,8 @@ MemCtrl::MemCtrl(const QoSMemCtrlParams * p)
     qosPriorityEscalation(p->qos_priority_escalation),
     qosSyncroScheduler(p->qos_syncro_scheduler),
     totalReadQueueSize(0), totalWriteQueueSize(0),
-    busState(READ), busStateNext(READ)
+    busState(READ), busStateNext(READ),
+    stats(*this)
 {
     // Set the priority policy
     if (policy) {
@@ -113,7 +114,7 @@ MemCtrl::logRequest(BusState dir, MasterID m_id, uint8_t qos,
     }
 
     // Record statistics
-    avgPriority[m_id].sample(qos);
+    stats.avgPriority[m_id].sample(qos);
 
     // Compute avg priority distance
 
@@ -122,7 +123,7 @@ MemCtrl::logRequest(BusState dir, MasterID m_id, uint8_t qos,
             (abs(int(qos) - int(i))) * packetPriorities[m_id][i];
 
         if (distance > 0) {
-            avgPriorityDistance[m_id].sample(distance);
+            stats.avgPriorityDistance[m_id].sample(distance);
             DPRINTF(QOS,
                     "QoSMemCtrl::logRequest MASTER %s [id %d]"
                     " registering priority distance %d for priority %d"
@@ -191,13 +192,13 @@ MemCtrl::logResponse(BusState dir, MasterID m_id, uint8_t qos,
 
         if (latency > 0) {
             // Record per-priority latency stats
-            if (priorityMaxLatency[qos].value() < latency) {
-                priorityMaxLatency[qos] = latency;
+            if (stats.priorityMaxLatency[qos].value() < latency) {
+                stats.priorityMaxLatency[qos] = latency;
             }
 
-            if (priorityMinLatency[qos].value() > latency
-                    || priorityMinLatency[qos].value() == 0) {
-                priorityMinLatency[qos] = latency;
+            if (stats.priorityMinLatency[qos].value() > latency
+                    || stats.priorityMinLatency[qos].value() == 0) {
+                stats.priorityMinLatency[qos] = latency;
             }
         }
     }
@@ -280,52 +281,71 @@ MemCtrl::addMaster(MasterID m_id)
     }
 }
 
+MemCtrl::MemCtrlStats::MemCtrlStats(MemCtrl &mc)
+    : Stats::Group(&mc),
+    memCtrl(mc),
+
+    ADD_STAT(avgPriority,
+             "Average QoS priority value for accepted requests"),
+    ADD_STAT(avgPriorityDistance,
+             "Average QoS priority distance between assigned and "
+             "queued values"),
+
+    ADD_STAT(priorityMinLatency,
+             "per QoS priority minimum request to response latency (s)"),
+    ADD_STAT(priorityMaxLatency,
+        "per QoS priority maximum request to response latency (s)"),
+    ADD_STAT(numReadWriteTurnArounds,
+             "Number of turnarounds from READ to WRITE"),
+    ADD_STAT(numWriteReadTurnArounds,
+             "Number of turnarounds from WRITE to READ"),
+    ADD_STAT(numStayReadState,
+             "Number of times bus staying in READ state"),
+    ADD_STAT(numStayWriteState,
+             "Number of times bus staying in WRITE state")
+{
+}
+
 void
-MemCtrl::regStats()
+MemCtrl::MemCtrlStats::regStats()
 {
-    AbstractMemory::regStats();
+    Stats::Group::regStats();
 
     using namespace Stats;
 
-    // Initializes per master statistics
-    avgPriority.init(_system->maxMasters()).name(name() + ".avgPriority")
-        .desc("Average QoS priority value for accepted requests")
-        .flags(nozero | nonan).precision(2);
-
-    avgPriorityDistance.init(_system->maxMasters())
-        .name(name() + ".avgPriorityDistance")
-        .desc("Average QoS priority distance between assigned and "
-        "queued values").flags(nozero | nonan);
-
-    priorityMinLatency.init(numPriorities())
-        .name(name() + ".priorityMinLatency")
-        .desc("per QoS priority minimum request to response latency (s)")
-        .precision(12);
+    System *system = memCtrl._system;
+    const auto max_masters = system->maxMasters();
+    const auto num_priorities = memCtrl.numPriorities();
 
-    priorityMaxLatency.init(numPriorities())
-        .name(name() + ".priorityMaxLatency")
-        .desc("per QoS priority maximum request to response latency (s)")
-        .precision(12);
-
-    numReadWriteTurnArounds.name(name() + ".numReadWriteTurnArounds")
-        .desc("Number of turnarounds from READ to WRITE");
-
-    numWriteReadTurnArounds.name(name() + ".numWriteReadTurnArounds")
-        .desc("Number of turnarounds from WRITE to READ");
-
-    numStayReadState.name(name() + ".numStayReadState")
-        .desc("Number of times bus staying in READ state");
-
-    numStayWriteState.name(name() + ".numStayWriteState")
-        .desc("Number of times bus staying in WRITE state");
-
-    for (int i = 0; i < _system->maxMasters(); i++) {
-        const std::string master = _system->getMasterName(i);
+    // Initializes per master statistics
+    avgPriority
+        .init(max_masters)
+        .flags(nozero | nonan)
+        .precision(2)
+        ;
+
+    avgPriorityDistance
+        .init(max_masters)
+        .flags(nozero | nonan)
+        ;
+
+    priorityMinLatency
+        .init(num_priorities)
+        .precision(12)
+        ;
+
+    priorityMaxLatency
+        .init(num_priorities)
+        .precision(12)
+        ;
+
+    for (int i = 0; i < max_masters; i++) {
+        const std::string master = system->getMasterName(i);
         avgPriority.subname(i, master);
         avgPriorityDistance.subname(i, master);
     }
 
-    for (int j = 0; j < numPriorities(); ++j) {
+    for (int j = 0; j < num_priorities; ++j) {
         priorityMinLatency.subname(j, std::to_string(j));
         priorityMaxLatency.subname(j, std::to_string(j));
     }
@@ -336,15 +356,15 @@ MemCtrl::recordTurnaroundStats()
 {
     if (busStateNext != busState) {
         if (busState == READ) {
-            numWriteReadTurnArounds++;
+            stats.numWriteReadTurnArounds++;
         } else if (busState == WRITE) {
-            numReadWriteTurnArounds++;
+            stats.numReadWriteTurnArounds++;
         }
     } else {
         if (busState == READ) {
-            numStayReadState++;
+            stats.numStayReadState++;
         } else if (busState == WRITE) {
-            numStayWriteState++;
+            stats.numStayWriteState++;
         }
     }
 }
diff --git a/src/mem/qos/mem_ctrl.hh b/src/mem/qos/mem_ctrl.hh
index db85f276d..e31f21b23 100644
--- a/src/mem/qos/mem_ctrl.hh
+++ b/src/mem/qos/mem_ctrl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -123,26 +123,35 @@ class MemCtrl: public AbstractMemory
     /** bus state for next request event triggered */
     BusState busStateNext;
 
-    /** per-master average QoS priority */
-    Stats::VectorStandardDeviation avgPriority;
-    /** per-master average QoS distance between assigned and queued values */
-    Stats::VectorStandardDeviation avgPriorityDistance;
-
-    /** per-priority minimum latency */
-    Stats::Vector priorityMinLatency;
-    /** per-priority maximum latency */
-    Stats::Vector priorityMaxLatency;
-    /** Count the number of turnarounds READ to WRITE */
-    Stats::Scalar numReadWriteTurnArounds;
-    /** Count the number of turnarounds WRITE to READ */
-    Stats::Scalar numWriteReadTurnArounds;
-    /** Count the number of times bus staying in READ state */
-    Stats::Scalar numStayReadState;
-    /** Count the number of times bus staying in WRITE state */
-    Stats::Scalar numStayWriteState;
-
-    /** registers statistics */
-    void regStats() override;
+    struct MemCtrlStats : public Stats::Group
+    {
+        MemCtrlStats(MemCtrl &mc);
+
+        void regStats() override;
+
+        const MemCtrl &memCtrl;
+
+        /** per-master average QoS priority */
+        Stats::VectorStandardDeviation avgPriority;
+        /**
+         * per-master average QoS distance between assigned and
+         * queued values
+         */
+        Stats::VectorStandardDeviation avgPriorityDistance;
+
+        /** per-priority minimum latency */
+        Stats::Vector priorityMinLatency;
+        /** per-priority maximum latency */
+        Stats::Vector priorityMaxLatency;
+        /** Count the number of turnarounds READ to WRITE */
+        Stats::Scalar numReadWriteTurnArounds;
+        /** Count the number of turnarounds WRITE to READ */
+        Stats::Scalar numWriteReadTurnArounds;
+        /** Count the number of times bus staying in READ state */
+        Stats::Scalar numStayReadState;
+        /** Count the number of times bus staying in WRITE state */
+        Stats::Scalar numStayWriteState;
+    } stats;
 
     /**
      * Initializes dynamically counters and