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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | d6736384b2bb280ec12d472cac6eb25a70b4af60 (patch) | |
| tree | 4ab72a9724a1f349a6c9ddc3088e73d7cebd7f90 /src/mem/request.hh | |
| parent | 23626d99af9469b5a86f510e0542846f5af65cbd (diff) | |
| download | gem5-d6736384b2bb280ec12d472cac6eb25a70b4af60.tar.xz | |
MEM: Make CLREX a first class request operation and clear locks in caches when it in received
Diffstat (limited to 'src/mem/request.hh')
| -rw-r--r-- | src/mem/request.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/request.hh b/src/mem/request.hh index 8d1697ad2..7149f3199 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -71,6 +71,8 @@ class Request : public FastAlloc static const FlagsType UNCACHEABLE = 0x00001000; /** This request is to a memory mapped register. */ static const FlagsType MMAPED_IPR = 0x00002000; + /** This request is a clear exclusive. */ + static const FlagsType CLREX = 0x00004000; /** The request should ignore unaligned access faults */ static const FlagsType NO_ALIGN_FAULT = 0x00020000; @@ -456,6 +458,7 @@ class Request : public FastAlloc bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); } bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); } bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); } + bool isClrex() const { return _flags.isSet(CLREX); } bool isMisaligned() const |