Merge zizzer:/z/m5/Bitkeeper/newmem

into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 6eefb4a3ee472f2f2c86ed823c70fc9e5625818f

1 files changed, 8 insertions, 0 deletions

diff --git a/src/mem/request.hh b/src/mem/request.hh
index af1d6d8a8..a1524f807 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -44,6 +44,7 @@ class Request;
 
 typedef Request* RequestPtr;
 
+
 /** The request is a Load locked/store conditional. */
 const unsigned LOCKED		= 0x001;
 /** The virtual address is also the physical address. */
@@ -62,6 +63,8 @@ const unsigned PF_EXCLUSIVE	= 0x100;
 const unsigned EVICT_NEXT	= 0x200;
 /** The request should ignore unaligned access faults */
 const unsigned NO_ALIGN_FAULT   = 0x400;
+/** The request was an instruction read. */
+const unsigned INST_READ        = 0x800;
 
 class Request
 {
@@ -224,6 +227,11 @@ class Request
     /** Accessor function for pc.*/
     Addr getPC() { assert(validPC); return pc; }
 
+    /** Accessor Function to Check Cacheability. */
+    bool isUncacheable() { return getFlags() & UNCACHEABLE; }
+
+    bool isInstRead() { return getFlags() & INST_READ; }
+
     friend class Packet;
 };