diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-12 13:06:30 -0500 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-12 13:06:30 -0500 |
commit | b5a4d95811db487d946200bf103e2af376db7690 (patch) | |
tree | 8004993f9ea05c8b78ba34930455fe671dff0e2d /src/mem/request.hh | |
parent | 1f834b569c8a39f44882c2f2010a9f0ecffdaab1 (diff) | |
download | gem5-b5a4d95811db487d946200bf103e2af376db7690.tar.xz |
rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic
src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
Diffstat (limited to 'src/mem/request.hh')
-rw-r--r-- | src/mem/request.hh | 31 |
1 files changed, 21 insertions, 10 deletions
diff --git a/src/mem/request.hh b/src/mem/request.hh index de0512e1c..43d8ff1d5 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -71,6 +71,10 @@ const uint32_t EVICT_NEXT = 0x20000; const uint32_t NO_ALIGN_FAULT = 0x40000; /** The request was an instruction read. */ const uint32_t INST_READ = 0x80000; +/** This request is for a memory swap. */ +const uint32_t MEM_SWAP = 0x100000; +const uint32_t MEM_SWAP_COND = 0x200000; + class Request { @@ -104,8 +108,9 @@ class Request /** The virtual address of the request. */ Addr vaddr; - /** The return value of store conditional. */ - uint64_t scResult; + /** Extra data for the request, such as the return value of + * store conditional or the compare value for a CAS. */ + uint64_t extraData; /** The cpu number (for statistics, typically). */ int cpuNum; @@ -120,7 +125,7 @@ class Request /** Whether or not the asid & vaddr are valid. */ bool validAsidVaddr; /** Whether or not the sc result is valid. */ - bool validScResult; + bool validExData; /** Whether or not the cpu number & thread ID are valid. */ bool validCpuAndThreadNums; /** Whether or not the pc is valid. */ @@ -130,7 +135,7 @@ class Request /** Minimal constructor. No fields are initialized. */ Request() : validPaddr(false), validAsidVaddr(false), - validScResult(false), validCpuAndThreadNums(false), validPC(false) + validExData(false), validCpuAndThreadNums(false), validPC(false) {} /** @@ -169,7 +174,7 @@ class Request validPaddr = true; validAsidVaddr = false; validPC = false; - validScResult = false; + validExData = false; mmapedIpr = false; } @@ -187,7 +192,7 @@ class Request validPaddr = false; validAsidVaddr = true; validPC = true; - validScResult = false; + validExData = false; mmapedIpr = false; } @@ -237,12 +242,12 @@ class Request void setMmapedIpr(bool r) { assert(validAsidVaddr); mmapedIpr = r; } /** Accessor function to check if sc result is valid. */ - bool scResultValid() { return validScResult; } + bool extraDataValid() { return validExData; } /** Accessor function for store conditional return value.*/ - uint64_t getScResult() { assert(validScResult); return scResult; } + uint64_t getExtraData() { assert(validExData); return extraData; } /** Accessor function for store conditional return value.*/ - void setScResult(uint64_t _scResult) - { scResult = _scResult; validScResult = true; } + void setExtraData(uint64_t _extraData) + { extraData = _extraData; validExData = true; } /** Accessor function for cpu number.*/ int getCpuNum() { assert(validCpuAndThreadNums); return cpuNum; } @@ -259,6 +264,12 @@ class Request bool isLocked() { return (getFlags() & LOCKED) != 0; } + bool isSwap() { return (getFlags() & MEM_SWAP || + getFlags() & MEM_SWAP_COND); } + + bool isCondSwap() { return (getFlags() & MEM_SWAP_COND) != 0; } + + friend class Packet; }; |