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author | Ali Saidi <saidi@eecs.umich.edu> | 2008-09-10 14:26:15 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2008-09-10 14:26:15 -0400 |
commit | 3a3e356f4e61e86f6f1427dd85cf1e41fa9125c0 (patch) | |
tree | c9e147a14bcab9e4767ad13a00ac4a375044c441 /src/mem/request.hh | |
parent | 09a8fb0b5263d4b41b8206ce075a3f6923907d65 (diff) | |
download | gem5-3a3e356f4e61e86f6f1427dd85cf1e41fa9125c0.tar.xz |
style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
Diffstat (limited to 'src/mem/request.hh')
-rw-r--r-- | src/mem/request.hh | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mem/request.hh b/src/mem/request.hh index 85ff8a445..ab8f9d596 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -53,21 +53,21 @@ typedef Request* RequestPtr; /** ASI information for this request if it exsits. */ const uint32_t ASI_BITS = 0x000FF; /** The request is a Load locked/store conditional. */ -const uint32_t LOCKED = 0x00100; +const uint32_t LOCKED = 0x00100; /** The virtual address is also the physical address. */ -const uint32_t PHYSICAL = 0x00200; +const uint32_t PHYSICAL = 0x00200; /** The request is an ALPHA VPTE pal access (hw_ld). */ -const uint32_t VPTE = 0x00400; +const uint32_t VPTE = 0x00400; /** Use the alternate mode bits in ALPHA. */ -const uint32_t ALTMODE = 0x00800; +const uint32_t ALTMODE = 0x00800; /** The request is to an uncacheable address. */ -const uint32_t UNCACHEABLE = 0x01000; +const uint32_t UNCACHEABLE = 0x01000; /** The request should not cause a page fault. */ const uint32_t NO_FAULT = 0x02000; /** The request should be prefetched into the exclusive state. */ -const uint32_t PF_EXCLUSIVE = 0x10000; +const uint32_t PF_EXCLUSIVE = 0x10000; /** The request should be marked as LRU. */ -const uint32_t EVICT_NEXT = 0x20000; +const uint32_t EVICT_NEXT = 0x20000; /** The request should ignore unaligned access faults */ const uint32_t NO_ALIGN_FAULT = 0x40000; /** The request was an instruction read. */ |