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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-28 17:28:33 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-28 17:28:33 -0400 |
| commit | 0d323c753d897bec72884089bc0dc334a64e9eb3 (patch) | |
| tree | b5c69c91860b1282cf2ef8a415ce965e51d94f4f /src/mem/request.hh | |
| parent | fc281d0b64fca8d2809ec462148acb7cf0461ea5 (diff) | |
| download | gem5-0d323c753d897bec72884089bc0dc334a64e9eb3.tar.xz | |
More Changes, working towards cache.cc compiling. Headers cleaned up.
src/mem/cache/cache_blk.hh:
Remove XC
--HG--
extra : convert_revision : aa2c43e4412ebb93165e12f693d5126983cfd0dc
Diffstat (limited to 'src/mem/request.hh')
| -rw-r--r-- | src/mem/request.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/request.hh b/src/mem/request.hh index 469184b13..46d9b6fd7 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -44,6 +44,7 @@ class Request; typedef Request* RequestPtr; + /** The request is a Load locked/store conditional. */ const unsigned LOCKED = 0x001; /** The virtual address is also the physical address. */ |