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| author | Daniel R. Carvalho <odanrc@yahoo.com.br> | 2019-09-07 11:14:57 +0200 |
|---|---|---|
| committer | Daniel Carvalho <odanrc@yahoo.com.br> | 2019-09-30 20:58:46 +0000 |
| commit | a5408244d1fb6dcad6234b601b5aa8d439fd49cd (patch) | |
| tree | 42a4d0d8e24510ddb6c19fde7ae70afd78be05a1 /src/mem/ruby/common/WriteMask.hh | |
| parent | 7ccf70a12196d7df31668166b0a3aa67a1106f61 (diff) | |
| download | gem5-a5408244d1fb6dcad6234b601b5aa8d439fd49cd.tar.xz | |
mem-ruby: Remove shiftLowOrderBits
There is no need to encapsulate a shift operation.
Change-Id: Ie711d8d4975d1d9dde656cc2284a048410cfdadb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21083
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/mem/ruby/common/WriteMask.hh')
0 files changed, 0 insertions, 0 deletions