merge

1 files changed, 39 insertions, 0 deletions

diff --git a/src/mem/ruby/config/MI_example.rb b/src/mem/ruby/config/MI_example.rb
new file mode 100644
index 000000000..187dc7a68
--- /dev/null
+++ b/src/mem/ruby/config/MI_example.rb
@@ -0,0 +1,39 @@
+
+require "util.rb"
+
+class MI_example_CacheController < L1CacheController
+  attr :cache
+  def initialize(obj_name, mach_type, cache, sequencer)
+    super(obj_name, mach_type, [cache], sequencer)
+    @cache = cache
+  end
+  def argv()
+    vec = super()
+    vec += " cache " + @cache.obj_name
+    vec += " issue_latency "+issue_latency.to_s
+    vec += " cache_response_latency "+cache_response_latency.to_s
+  end
+
+end
+
+class MI_example_DirectoryController < DirectoryController
+  def initialize(obj_name, mach_type, directory, memory_control)
+    super(obj_name, mach_type, directory, memory_control)
+  end
+  def argv()
+    vec = super()
+    vec += " directory_latency "+directory_latency.to_s
+    vec += " dma_select_low_bit "+log_int(RubySystem.block_size_bytes).to_s
+    vec += " dma_select_num_bits "+log_int(NetPort.totalOfType("DMA")).to_s
+  end
+end
+
+class MI_example_DMAController < DMAController
+  def initialize(obj_name, mach_type, dma_sequencer)
+    super(obj_name, mach_type, dma_sequencer)
+  end
+  def argv()
+    vec = super
+    vec += " request_latency "+request_latency.to_s
+  end
+end