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authorDerek Hower <drh5@cs.wisc.edu>2009-08-05 14:20:32 -0500
committerDerek Hower <drh5@cs.wisc.edu>2009-08-05 14:20:32 -0500
commitfbf7391bb0aa3c32289abb8a1b1066267df7c705 (patch)
treee05f36245b08938be2c87c29ef97c8f349e02956 /src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
parent1276df51e245c6e836d7e96c0df66a7b74b549c9 (diff)
downloadgem5-fbf7391bb0aa3c32289abb8a1b1066267df7c705.tar.xz
ruby: configuration supports multiple runs in same session
These changes allow to run Ruby-gems multiple times from the same ruby-lang script with different configurations
Diffstat (limited to 'src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb')
-rw-r--r--src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb30
1 files changed, 16 insertions, 14 deletions
diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
index 11cb7fb57..8a202d450 100644
--- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
+++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
@@ -7,22 +7,24 @@
require "cfg.rb"
+RubySystem.reset
+
# default values
num_cores = 2
-L1_ICACHE_SIZE_KB = 32
-L1_ICACHE_ASSOC = 8
-L1_ICACHE_LATENCY = 1
-L1_DCACHE_SIZE_KB = 32
-L1_DCACHE_ASSOC = 8
-L1_DCACHE_LATENCY = 1
-L2_CACHE_SIZE_KB = 2048 # total size (sum of all banks)
-L2_CACHE_ASSOC = 16
-L2_CACHE_LATENCY = 12
+l1_icache_size_kb = 32
+l1_icache_assoc = 8
+l1_icache_latency = 1
+l1_dcache_size_kb = 32
+l1_dcache_assoc = 8
+l1_dcache_latency = 1
+l2_cache_size_kb = 2048 # total size (sum of all banks)
+l2_cache_assoc = 16
+l2_cache_latency = 12
num_l2_banks = num_cores
num_memories = 1
memory_size_mb = 1024
-NUM_DMA = 1
+num_dma = 1
protocol = "MOESI_CMP_directory"
@@ -52,8 +54,8 @@ assert(protocol == "MOESI_CMP_directory", __FILE__+" cannot be used with protoco
require protocol+".rb"
num_cores.times { |n|
- icache = SetAssociativeCache.new("l1i_"+n.to_s, L1_ICACHE_SIZE_KB, L1_ICACHE_LATENCY, L1_ICACHE_ASSOC, "PSEUDO_LRU")
- dcache = SetAssociativeCache.new("l1d_"+n.to_s, L1_DCACHE_SIZE_KB, L1_DCACHE_LATENCY, L1_DCACHE_ASSOC, "PSEUDO_LRU")
+ icache = SetAssociativeCache.new("l1i_"+n.to_s, l1_icache_size_kb, l1_icache_latency, l1_icache_assoc, "PSEUDO_LRU")
+ dcache = SetAssociativeCache.new("l1d_"+n.to_s, l1_dcache_size_kb, l1_dcache_latency, l1_dcache_assoc, "PSEUDO_LRU")
sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache)
iface_ports << sequencer
if protocol == "MOESI_CMP_directory"
@@ -65,7 +67,7 @@ num_cores.times { |n|
end
}
num_l2_banks.times { |n|
- cache = SetAssociativeCache.new("l2u_"+n.to_s, L2_CACHE_SIZE_KB/num_l2_banks, L2_CACHE_LATENCY, L2_CACHE_ASSOC, "PSEUDO_LRU")
+ cache = SetAssociativeCache.new("l2u_"+n.to_s, l2_cache_size_kb/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU")
if protocol == "MOESI_CMP_directory"
net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
"L2Cache",
@@ -82,7 +84,7 @@ num_memories.times { |n|
memory_control)
end
}
-NUM_DMA.times { |n|
+num_dma.times { |n|
dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
iface_ports << dma_sequencer
if protocol == "MOESI_CMP_directory"