slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate.  They are:

1.  Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller.  I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2.  DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well.  It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc.  Currently, only int parameters are supported.

1 files changed, 36 insertions, 45 deletions

diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb
index a43b5e125..82fbb64a5 100644
--- a/src/mem/ruby/config/cfg.rb
+++ b/src/mem/ruby/config/cfg.rb
@@ -233,6 +233,7 @@ class RubySystem
       end
     }
     str += LibRubyObject.printConstructors
+    #puts str.gsub('%',' ').gsub('#','\n')
     return str
   end
 
@@ -287,35 +288,33 @@ end
 
 
 class CacheController < NetPort
-  @@total_cache_controllers = 0
-  attr :caches
-  attr :sequencer
-  def initialize(obj_name, mach_type, caches, sequencer)
+  @@total_cache_controllers = Hash.new
+
+  def initialize(obj_name, mach_type, caches)
     super(obj_name, mach_type)
-    @caches = caches
-    @caches.each { |cache|
+    caches.each { |cache|
       cache.controller = self
     }
 
-    @sequencer = sequencer
-    @sequencer.controller = self
-
-    @version = @@total_cache_controllers
-    @@total_cache_controllers += 1
-    @sequencer.version = @version
-    buffer_size()
+    if !@@total_cache_controllers.has_key?(mach_type)
+      @@total_cache_controllers[mach_type] = 0
+    end
+    @version = @@total_cache_controllers[mach_type]
+    @@total_cache_controllers[mach_type] += 1
+    
+    # call inhereted parameters
+    transitions_per_cycle
+    buffer_size
+    number_of_TBEs
+    recycle_latency
   end
 
   def argv()
     vec = "version "+@version.to_s
-    @caches.each { |cache|
-      vec += " cache " + cache.obj_name
-    }
-    vec += " sequencer "+@sequencer.obj_name
     vec += " transitions_per_cycle "+@params[:transitions_per_cycle].to_s
     vec += " buffer_size "+@params[:buffer_size].to_s
     vec += " number_of_TBEs "+@params[:number_of_TBEs].to_s
-
+    vec += " recycle_latency "+@params[:recycle_latency].to_s
   end
 
   def cppClassName()
@@ -323,6 +322,23 @@ class CacheController < NetPort
   end
 end
 
+class L1CacheController < CacheController
+  attr :sequencer
+
+  def initialize(obj_name, mach_type, caches, sequencer)
+    super(obj_name, mach_type, caches)
+
+    @sequencer = sequencer
+    @sequencer.controller = self
+    @sequencer.version = @version
+  end
+
+  def argv()
+    vec = super()
+    vec += " sequencer "+@sequencer.obj_name
+  end
+end
+
 class DirectoryController < NetPort
   @@total_directory_controllers = 0
   attr :directory
@@ -364,7 +380,7 @@ class DMAController < NetPort
   end
 
   def argv()
-    "version "+@version.to_s+" dma_sequencer "+@dma_sequencer.obj_name+" transitions_per_cycle "+@params[:transitions_per_cycle].to_s + " buffer_size "+@params[:buffer_size].to_s + " number_of_TBEs "+@params[:number_of_TBEs].to_s
+    "version "+@version.to_s+" dma_sequencer "+@dma_sequencer.obj_name+" transitions_per_cycle "+@params[:transitions_per_cycle].to_s + " buffer_size "+@params[:buffer_size].to_s + " number_of_TBEs "+@params[:number_of_TBEs].to_s +  " recycle_latency "+@params[:recycle_latency].to_s
   end
 
   def cppClassName()
@@ -606,7 +622,7 @@ class Network < LibRubyObject
   end
 
   def printTopology()
-    topology.printFile
+    topology().printFile
   end
   def cppClassName()
     "SimpleNetwork"
@@ -686,31 +702,6 @@ class Profiler < LibRubyObject
 
 end
 
-class MI_example_CacheController < CacheController
-  def initialize(obj_name, mach_type, caches, sequencer)
-    super(obj_name, mach_type, caches, sequencer)
-  end
-  def argv()
-    vec = super()
-    vec += " issue_latency "+issue_latency.to_s
-    vec += " cache_response_latency "+cache_response_latency.to_s
-  end
-
-end
-
-class MI_example_DirectoryController < DirectoryController
-  def initialize(obj_name, mach_type, directory, memory_control)
-    super(obj_name, mach_type, directory, memory_control)
-  end
-  def argv()
-    vec = super()
-    vec += " to_mem_ctrl_latency "+to_mem_ctrl_latency.to_s
-    vec += " directory_latency "+directory_latency.to_s
-    vec += " memory_latency "+memory_latency.to_s
-  end
-
-end
-
 #added by SS
 class GarnetNetwork < Network
   def initialize(name, topo)